Low Latency 100-Gbps Ethernet IP Core User Guide

ID 683160
Date 4/15/2021
Public
Document Table of Contents

3.2.18. Arria 10 Transceiver Reconfiguration Interface

Arria 10 variations provide a dedicated Avalon-MM interface, called the Arria 10 transceiver reconfiguration interface, to access the transceiver registers. You access the Arria 10 Native PHY IP core registers through this dedicated interface and not through the IP core general purpose control and status interface.

The Avalon-MM interface implements a standard memory-mapped protocol. You can connect an embedded processor or JTAG Avalon master to this bus to access the registers of the embedded Arria 10 Native PHY IP core.

Table 26.  Avalon-MM Arria 10 Reconfiguration Interface SignalsThe reconfig_clk clocks the signals on the LL 100GbE IP core Arria 10 transceiver reconfiguration interface. The synchronous reconfig_reset reset signal resets the interface.

Signal Name

Direction

Description

reconfig_address [13:0]

reconfig_address [11:0] (CAUI-4)

Input

Address for reads and writes

reconfig_read

Input

Read command

reconfig_write

Input

Write command

reconfig_writedata [31:0]

Input

Data to be written

reconfig_readdata [31:0]

Output

Read data

reconfig_waitrequest

Output

Interface busy signal

The Arria 10 reconfiguration interface is designed to operate at a low frequency, 100 MHz to 125 MHz, so that the user's Arria 10 transceiver reconfiguration logic does not compete for resources with the surrounding high speed datapath.

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