Low Latency 100-Gbps Ethernet IP Core User Guide

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ID 683160
Date 4/15/2021
Public
Document Table of Contents

3.2.16. Transceiver PHY Serial Data Interface

The core uses an <n>-lane digital interface to send data to the TX high-speed serial I/O pins operating at 10.3125 Gbps in the standard LL 100GbE variations and at 25.78125 Gbps in the CAUI–4 variations. The rx_serial and tx_serial ports connect to the 10.3125 Gbps or 25.78125 Gbps pins. Virtual lanes 0 and 1 transmit data on tx_serial[0].

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