Low Latency 100-Gbps Ethernet IP Core User Guide

ID 683160
Date 4/15/2021
Public
Document Table of Contents

3. Functional Description

This chapter provides a detailed description of the LL 100GbE IP core. The chapter begins with a high-level overview of typical Ethernet systems and then provides detailed descriptions of the MAC, transmit (TX) and receive (RX) datapaths, signals, register descriptions, and an Ethernet glossary. This chapter includes the following sections:

Did you find the information on this page useful?

Characters remaining:

Feedback Message