Low Latency 100-Gbps Ethernet IP Core User Guide

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ID 683160
Date 4/15/2021
Public
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2.7.4. Handling Potential Jitter in Intel® Arria® 10 Devices

The RX path in the LL 100GbE core includes cascaded PLLs. Therefore, the IP core clocks might experience additional jitter in Intel® Arria® 10 devices.

Refer to the KDB Answer How do I compensate for the jitter of PLL cascading or non-dedicated clock path for Arria 10 PLL reference clock? for a workaround you should apply to the IP core, in your design.

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