Low Latency 100-Gbps Ethernet IP Core User Guide

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ID 683160
Date 4/15/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the LL 100GbE IP Core 2. Getting Started 3. Functional Description 4. Debugging the Link A. Additional Information
1. About the LL 100GbE IP Core x
1.1. LL 100GbE IP Core Supported Features 1.2. IP Core Device Family and Speed Grade Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Release Information
1.2. IP Core Device Family and Speed Grade Support x
1.2.1. LL 100GbE IP Core Device Family Support 1.2.2. LL 100GbE IP Core Device Speed Grade Support
1.3. IP Core Verification x
1.3.1. Simulation Environment 1.3.2. Compilation Checking 1.3.3. Hardware Testing
1.4. Performance and Resource Utilization x
1.4.1. Arria 10 Resource Utilization 1.4.2. Stratix V Resource Utilization
2. Getting Started x
2.1. Installation and Licensing for LL 100GbE IP Core for Stratix® V Devices 2.2. Installing and Licensing Intel® FPGA IP Cores 2.3. Specifying the IP Core Parameters and Options 2.4. IP Core Parameters 2.5. Files Generated for Stratix V Variations 2.6. Files Generated for Arria 10 Variations 2.7. Integrating Your IP Core in Your Design 2.8. IP Core Testbenches 2.9. Compiling the Full Design and Programming the FPGA 2.10. Initializing the IP Core
2.2. Installing and Licensing Intel® FPGA IP Cores x
2.2.1. Intel® FPGA IP Evaluation Mode
2.7. Integrating Your IP Core in Your Design x
2.7.1. Pin Assignments 2.7.2. External Transceiver Reconfiguration Controller Required in Stratix V Designs 2.7.3. Transceiver PLL Required in Arria 10 Designs 2.7.4. Handling Potential Jitter in Intel® Arria® 10 Devices 2.7.5. External Time-of-Day Module for Variations with 1588 PTP Feature 2.7.6. External TX MAC PLL 2.7.7. Placement Settings for the LL 100GbE Core
2.8. IP Core Testbenches x
2.8.1. Testbench Behavior 2.8.2. Simulating the LL 100GbE IP Core With the Testbenches
2.8.2. Simulating the LL 100GbE IP Core With the Testbenches x
2.8.2.1. Generating the LL 100GbE Testbench 2.8.2.2. Optimizing the IP Core Simulation With the Testbenches 2.8.2.3. Simulating with the Modelsim Simulator 2.8.2.4. Simulating with the NCSim Simulator 2.8.2.5. Simulating with the VCS Simulator 2.8.2.6. Testbench Output Example
3. Functional Description x
3.1. High Level System Overview 3.2. LL 100GbE IP Core Functional Description 3.3. Signals 3.4. Software Interface: Registers 3.5. Ethernet Glossary
3.2. LL 100GbE IP Core Functional Description x
3.2.1. LL 100GbE IP Core TX Datapath 3.2.2. LL 100GbE IP Core TX Data Bus Interfaces 3.2.3. LL 100GbE IP Core RX Datapath 3.2.4. LL 100GbE IP Core RX Data Bus Interfaces 3.2.5. Low Latency 100GbE CAUI–4 PHY 3.2.6. External Reconfiguration Controller 3.2.7. External Transceiver PLL 3.2.8. External TX MAC PLL 3.2.9. Congestion and Flow Control Using Pause Frames 3.2.10. Pause Control and Generation Interface 3.2.11. Pause Control Frame Filtering 3.2.12. Link Fault Signaling Interface 3.2.13. Statistics Counters Interface 3.2.14. 1588 Precision Time Protocol Interfaces 3.2.15. PHY Status Interface 3.2.16. Transceiver PHY Serial Data Interface 3.2.17. Control and Status Interface 3.2.18. Arria 10 Transceiver Reconfiguration Interface 3.2.19. Clocks 3.2.20. Resets
3.2.1. LL 100GbE IP Core TX Datapath x
3.2.1.1. Preamble, Start, and SFD Insertion 3.2.1.2. Address Insertion 3.2.1.3. Length/Type Field Processing 3.2.1.4. Frame Padding 3.2.1.5. Frame Check Sequence (CRC-32) Insertion 3.2.1.6. Inter-Packet Gap Generation and Insertion 3.2.1.7. TX RSFEC 3.2.1.8. Error Insertion Test and Debug Feature
3.2.2. LL 100GbE IP Core TX Data Bus Interfaces x
3.2.2.1. LL 100GbE IP Core User Interface Data Bus 3.2.2.2. LL 100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface) 3.2.2.3. LL 100GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface) 3.2.2.4. Bus Quantization Effects With Adapters 3.2.2.5. User Interface to Ethernet Transmission
3.2.2.5. User Interface to Ethernet Transmission x
3.2.2.5.1. Order of Transmission
3.2.3. LL 100GbE IP Core RX Datapath x
3.2.3.1. LL 100GbE IP Core RX Filtering 3.2.3.2. LL 100GbE IP Core Preamble Processing 3.2.3.3. LL 100GbE IP Core FCS (CRC-32) Removal 3.2.3.4. LL 100GbE IP Core CRC Checking 3.2.3.5. LL 100GbE IP Core Malformed Packet Handling 3.2.3.6. RX CRC Forwarding 3.2.3.7. Inter-Packet Gap 3.2.3.8. RX RSFEC 3.2.3.9. Pause Ignore 3.2.3.10. Control Frame Identification
3.2.4. LL 100GbE IP Core RX Data Bus Interfaces x
3.2.4.1. LL 100GbE IP Core User Interface Data Bus 3.2.4.2. LL 100GbE IP Core RX Data Bus with Adapters (Avalon-ST Interface) 3.2.4.3. LL 100GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface)
3.2.9. Congestion and Flow Control Using Pause Frames x
3.2.9.1. Conditions Triggering XOFF Frame Transmission 3.2.9.2. Conditions Triggering XON Frame Transmission
3.2.13. Statistics Counters Interface x
3.2.13.1. OctetOK Count Interface
3.2.14. 1588 Precision Time Protocol Interfaces x
3.2.14.1. Implementing a 1588 System That Includes a LL 100GbE Core 3.2.14.2. PTP Receive Functionality 3.2.14.3. PTP Transmit Functionality 3.2.14.4. External Time-of-Day Module for 1588 PTP Variations 3.2.14.5. PTP Timestamp and TOD Formats 3.2.14.6. 1588 PTP Interface Signals
3.3. Signals x
3.3.1. LL 100GbE IP Core Signals
3.4. Software Interface: Registers x
3.4.1. LL 100GbE IP Core Registers 3.4.2. LL 100GbE Hardware Design Example Registers
3.4.1. LL 100GbE IP Core Registers x
3.4.1.1. PHY Registers 3.4.1.2. Link Fault Signaling Registers 3.4.1.3. LL 100GbE IP Core MAC Configuration Registers 3.4.1.4. Pause Registers 3.4.1.5. TX Statistics Registers 3.4.1.6. RX Statistics Registers 3.4.1.7. 1588 PTP Registers 3.4.1.8. TX Reed-Solomon FEC Registers 3.4.1.9. RX Reed-Solomon FEC Registers
3.4.2. LL 100GbE Hardware Design Example Registers x
3.4.2.1. Packet Client Registers
4. Debugging the Link x
4.1. Creating a Signal Tap Debug File to Match Your Design Hierarchy
A. Additional Information x
A.1. LL 100GbE IP Core User Guide Archives A.2. LL 100GbE IP Core User Guide Revision History
1. About the LL 100GbE IP Core
2. Getting Started
3. Functional Description
4. Debugging the Link
A. Additional Information

3.4.1.5. TX Statistics Registers

The TX statistics registers count TX Ethernet traffic and errors. The 64-bit statistics registers are designed to roll over, to ensure timing closure on the FPGA. However, these registers should never roll over if the link is functioning properly. The statistics registers check the size of frames, which includes the following fields:

  • Size of the destination address
  • Size of the source address
  • Size of the data
  • Four bytes of CRC

The TX statistics counters module is a synthesis option. The statistics registers are counters that are implemented inside the CSR. When you turn on the Enable TX statistics parameter in the LL 100GbE parameter editor, the counters are implemented in the CSR. When you turn off the Enable TX statistics parameter in the LL 100GbE parameter editor, the counters are not implemented in the CSR, and read access to the counters returns read data equal to 0.

Reading the value of a statistics register does not affect its value. A configuration register at offset 0x845 allows you to clear all of the TX statistics counters.

To ensure that the counters you read are consistent, you should issue a shadow request to create a snapshot of all of the TX statistics registers, by setting bit [2] of the configuration register at offset 0x845. Until you reset this bit, the counters continue to increment but the readable values remain constant.

Table 41.  Transmit Side Statistics Registers

Address

Name-

Description

Access

0x800

CNTR_TX_FRAGMENTS_LO

Number of transmitted frames less than 64 bytes and reporting a CRC error (lower 32 bits)

RO

0x801

CNTR_TX_FRAGMENTS_HI

Number of transmitted frames less than 64 bytes and reporting a CRC error (upper 32 bits)

RO

0x802

CNTR_TX_JABBERS_LO

Number of transmitted oversized frames reporting a CRC error (lower 32 bits)

RO

0x803

CNTR_TX_JABBERS_HI

Number of transmitted oversized frames reporting a CRC error (upper 32 bits)

RO

0x804

CNTR_TX_FCS_LO

Number of transmitted packets with FCS errors. (lower 32 bits)

RO

0x805

CNTR_TX_FCS_HI

Number of transmitted packets with FCS errors. (upper 32 bits)

RO

0x806

CNTR_TX_CRCERR_LO

Number of transmitted frames with a frame of length at least 64 reporting a CRC error (lower 32 bits)

RO

0x807

CNTR_TX_CRCERR_HI

Number of transmitted frames with a frame of length at least 64 reporting a CRC error (upper 32 bits)

RO

0x808

CNTR_TX_MCAST_DATA_ERR_LO

Number of errored multicast frames transmitted, excluding control frames (lower 32 bits)

RO

0x809

CNTR_TX_MCAST_DATA_ERR_HI

Number of errored multicast frames transmitted, excluding control frames (upper 32 bits)

RO

0x80A

CNTR_TX_BCAST_DATA_ERR_LO

Number of errored broadcast frames transmitted, excluding control frames (lower 32 bits)

RO

0x80B

CNTR_TX_BCAST_DATA_ERR_HI

Number of errored broadcast frames transmitted, excluding control frames (upper 32 bits)

RO

0x80C

CNTR_TX_UCAST_DATA_ERR_LO

Number of errored unicast frames transmitted, excluding control frames (lower 32 bits)

RO

0x80D

CNTR_TX_UCAST_DATA_ERR_HI

Number of errored unicast frames transmitted, excluding control frames (upper 32 bits)

RO

0x80E

CNTR_TX_MCAST_CTRL_ERR_LO

Number of errored multicast control frames transmitted (lower 32 bits)

RO

0x80F

CNTR_TX_MCAST_CTRL_ERR_HI

Number of errored multicast control frames transmitted (upper 32 bits)

RO

0x810

CNTR_TX_BCAST_CTRL_ERR_LO

Number of errored broadcast control frames transmitted (lower 32 bits)

RO

0x811

CNTR_TX_BCAST_CTRL_ERR_HI

Number of errored broadcast control frames transmitted (upper 32 bits)

RO

0x812

CNTR_TX_UCAST_CTRL_ERR_LO

Number of errored unicast control frames transmitted (lower 32 bits)

RO

0x813

CNTR_TX_UCAST_CTRL_ERR_HI

Number of errored unicast control frames transmitted (upper 32 bits)

RO

0x814

CNTR_TX_PAUSE_ERR_LO

Number of errored pause frames transmitted (lower 32 bits)

RO

0x815

CNTR_TX_PAUSE_ERR_HI

Number of errored pause frames transmitted (upper 32 bits)

RO

0x816

CNTR_TX_64B_LO

Number of 64-byte transmitted frames (lower 32 bits), including the CRC field but excluding the preamble and SFD bytes

RO

0x817

CNTR_TX_64B_HI

Number of 64-byte transmitted frames (upper 32 bits), including the CRC field but excluding the preamble and SFD bytes

RO

0x818

CNTR_TX_65to127B_LO

Number of transmitted frames between 65–127 bytes (lower 32 bits)

RO

0x819

CNTR_TX_65to127B_HI

Number of transmitted frames between 65–127 bytes (upper 32 bits)

RO

0x81A

CNTR_TX_128to255B_LO

Number of transmitted frames between 128 –255 bytes (lower 32 bits)

RO

0x81B

CNTR_TX_128to255B_HI

Number of transmitted frames between 128 –255 bytes (upper 32 bits)

RO

0x81C

CNTR_TX_256to511B_LO

Number of transmitted frames between 256 –511 bytes (lower 32 bits)

RO

0x81D

CNTR_TX_256to511B_HI

Number of transmitted frames between 256 –511 bytes (upper 32 bits)

RO

0x81E

CNTR_TX_512to1023B_LO

Number of transmitted frames between 512–1023 bytes (lower 32 bits)

RO

0x81F

CNTR_TX_512to1023B_HI

Number of transmitted frames between 512 –1023 bytes (upper 32 bits)

RO

0x820

CNTR_TX_1024to1518B_LO

Number of transmitted frames between 1024–1518 bytes (lower 32 bits)

RO

0x821

CNTR_TX_1024to1518B_HI

Number of transmitted frames between 1024–1518 bytes (upper 32 bits)

RO

0x822

CNTR_TX_1519toMAXB_LO

Number of transmitted frames of size between 1519 bytes and the number of bytes specified in the MAX_TX_SIZE_CONFIG register (lower 32 bits)

RO

0x823

CNTR_TX_1519toMAXB_HI

Number of transmitted frames of size between 1519 bytes and the number of bytes specified in the MAX_TX_SIZE_CONFIG register (upper 32 bits)

RO

0x824

CNTR_TX_OVERSIZE_LO

Number of oversized frames (frames with more bytes than the number specified in the MAX_TX_SIZE_CONFIG register) transmitted (lower 32 bits)

RO

0x825

CNTR_TX_OVERSIZE_HI

Number of oversized frames (frames with more bytes than the number specified in the MAX_TX_SIZE_CONFIG register) transmitted (upper 32 bits)

RO

0x826

CNTR_TX_MCAST_DATA_OK_LO

Number of valid multicast frames transmitted, excluding control frames (lower 32 bits)

RO

0x827

CNTR_TX_MCAST_DATA_OK_HI

Number of valid multicast frames transmitted, excluding control frames (upper 32 bits)

RO

0x828

CNTR_TX_BCAST_DATA_OK_LO

Number of valid broadcast frames transmitted, excluding control frames (lower 32 bits)

RO

0x829

CNTR_TX_BCAST_DATA_OK_HI

Number of valid broadcast frames transmitted, excluding control frames (upper 32 bits)

RO

0x82A

CNTR_TX_UCAST_DATA_OK_LO

Number of valid unicast frames transmitted, excluding control frames (lower 32 bits)

RO

0x82B

CNTR_TX_UCAST_DATA_OK_HI

Number of valid unicast frames transmitted, excluding control frames (upper 32 bits)

RO

0x82C

CNTR_TX_MCAST_CTRL_LO

Number of valid multicast frames transmitted, excluding data frames (lower 32 bits)

RO

0x82D

CNTR_TX_MCAST_CTRL_HI

Number of valid multicast frames transmitted, excluding data frames (upper 32 bits)

RO

0x82E

CNTR_TX_BCAST_CTRL_LO

Number of valid broadcast frames transmitted, excluding data frames (lower 32 bits)

RO

0x82F

CNTR_TX_BCAST_CTRL_HI

Number of valid broadcast frames transmitted, excluding data frames (upper 32 bits)

RO

0x830

CNTR_TX_UCAST_CTRL_LO

Number of valid unicast frames transmitted, excluding data frames (lower 32 bits)

RO

0x831

CNTR_TX_UCAST_CTRL_HI

Number of valid unicast frames transmitted, excluding data frames (upper 32 bits)

RO

0x832

CNTR_TX_PAUSE_LO

Number of valid pause frames transmitted (lower 32 bits)

RO

0x833

CNTR_TX_PAUSE_HI

Number of valid pause frames transmitted (upper 32 bits)

RO

0x834

CNTR_TX_RUNT_LO

Number of transmitted runt packets (lower 32 bits). The IP core does not transmit frames of length less than nine bytes. The IP core pads frames of length nine bytes to 64 bytes to extend them to 64 bytes.

RO

0x835

CNTR_TX_RUNT_HI

Number of transmitted runt packets (upper 32 bits). The IP core does not transmit frames of length less than nine bytes. The IP core pads frames of length nine bytes to 64 bytes to extend them to 64 bytes.

RO

0x836

CNTR_TX_ST_LO

Number of transmitted frame starts (lower 32 bits)

RO

0x837

CNTR_TX_ST_HI

Number of transmitted frame starts (upper 32 bits)

RO

0x838–0x83F

Reserved

0x840 TXSTAT_REVID TX statistics module revision ID. RO
0x841 TXSTAT_SCRATCH Scratch register available for testing. Default value is 0x08. RW
0x842 TXSTAT_NAME_0 First 4 characters of IP core variation identifier string "100gMacStats" RO
0x843 TXSTAT_NAME_1 Next 4 characters of IP core variation identifier string "100gMacStats" RO
0x844 TXSTAT_NAME_2 Final 4 characters of IP core variation identifier string "100gMacStats" RO
0x845

CNTR_TX_CONFIG

Bits [2:0]: Configuration of TX statistics counters:

  • Bit [2]: Shadow request (active high): When set to the value of 1, TX statistics collection is paused. The underlying counters continue to operate, but the readable values reflect a snapshot at the time the pause flag was activated. Write a 0 to release.
  • Bit [1]: Parity-error clear. When software sets this bit, the IP core clears the parity bit CNTR_TX_STATUS[0]. This bit (CNTR_TX_CONFIG[1]) is self-clearing.
  • Bit [0]: Software can set this bit to the value of 1 to reset all of the TX statistics registers at the same time. This bit is self-clearing.

Bits [31:3] are Reserved.

RW

0x846

CNTR_TX_STATUS

  • Bit [1]: Indicates that the TX statistics registers are paused (while CNTR_TX_CONFIG[2] is asserted) .
  • Bit [0]: Indicates the presence of at least one parity error in the TX statistics counters.

Bits [31:2] are Reserved.

RO
0x860 TxOctetsOK_LO Number of transmitted payload bytes in frames with no FCS, undersized, oversized, or payload length errors. This register is compliant with section 5.2.2.18 of the IEEE Standard 802.3-2008.

This register corresponds to the signals tx_inc_octetsOK[15:0] and tx_inc_octetsOK_valid.

RO
0x861 TxOctetsOK_HI RO
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