Low Latency 100-Gbps Ethernet IP Core User Guide

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ID 683160
Date 4/15/2021
Public
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3.2.3.4. LL 100GbE IP Core CRC Checking

The 32-bit CRC field is received in the order: X32, X30, . . . X1, and X0 , where X32 is the most significant bit of the FCS field and occupies the least significant bit position in the first FCS byte.

If a CRC32 error is detected, the RX MAC marks the frame invalid by asserting the l8_rx_fcs_error and l8_rx_fcs_valid (or rx_fcs_error and rx_fcs_valid) signals, as well as the l8_rx_error[1] (or rx_error[1]) signal.

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