Low Latency 100-Gbps Ethernet IP Core User Guide

ID 683160
Date 4/15/2021
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3.4.1.7. 1588 PTP Registers

The 1588 PTP registers together with the 1588 PTP signals process and provide Precision Time Protocol (PTP) timestamp information as defined in the IEEE 1588-2008 Precision Clock Synchronization Protocol for Networked Measurement and Control Systems Standard. The 1588 PTP module provides you the support to implement the 1588 Precision Time Protocol in your design.

Table 43.  TX 1588 PTP Registers

Addr

Name

Bit

Description

HW Reset Value

Access

0xA00 TXPTP_REVID [31:0] IP core revision ID. 0x0916_2016 RO
0xA01 TXPTP_SCRATCH [31:0] Scratch register available for testing. 32'b0 RW
0xA02 TXPTP_NAME_0 [31:0] First 4 characters of IP core variation identifier string.

0x7843_5352

RO
0xA03 TXPTP_NAME_1 [31:0] Next 4 characters of IP core variation identifier string.

0x5054_5054

RO
0xA04 TXPTP_NAME_2 [31:0] Final 4 characters of IP core variation identifier string.

0x3034_3067

RO
0xA05 TX_PTP_CLK_PERIOD [19:0] clk_txmac clock period.

Bits [19:16]: nanoseconds

Bits [15:0]: fraction of nanosecond

This value is set to the correct clock period for the required TX MAC clock frequency. RW

0xA06–0xA09

Reserved   Reserved 96'b0 RO
0xA0A TX_PTP_EXTRA_LATENCY [31:0] User-defined extra latency the IP core adds to outgoing timestamps.

Bits [31:16]: Full nanoseconds

Bits [15:0]: fraction of nanosecond

32'b0 RW
0xA0B TX_PTP_ASYM_DELAY [18:0] Asymmetry adjustment as required for delay measurement. The IP core adds this value to the final delay.
  • Bit[18]: The value of 1 enables the feature and the value of 0 disables the feature.
  • Bit[17]: The value of 1 indicates subtraction and the value of 0 indicates addition. Depending on the value of this bit, the value in bits [16:0] is added to or subtracted from the final delay.
  • Bits[16:0]: Asymmetry adjustment in nanoseconds.
19'b0 RW
0xA0C TX_PTP_PMA_LATENCY [31:0] Latency through the TX PMA. This is the delay from the TX PCS output to the tx_serial pins.
  • Bits [31:16]: Full nanoseconds
  • Bits [15:0]: Fraction of a nanosecond

In Arria 10 devices, the TX PMA latency is 187 UI. One UI is approximately 38.8 ps.

Therefore, Intel recommends that you set this register to the value of 0x0007_428F . This is a device-dependent value that is sufficiently accurate in most cases. Intel recommends that you modify this value with extreme caution.

32'b0 RW
Table 44.  RX 1588 PTP Registers

Addr

Name

Bit

Description

HW Reset Value

Access

0xB00 RXPTP_REVID [31:0] IP core revision ID. 0x0916_2016 RO
0xB01 RXPTP_SCRATCH [31:0] Scratch register available for testing. 32'b0 RW
0xB02 RXPTP_NAME_0 [31:0] First 4 characters of IP core variation identifier string.

0x7843_5352

RO
0xB03 RXPTP_NAME_1 [31:0] Next 4 characters of IP core variation identifier string

0x5054_5054

RO
0xB04 RXPTP_NAME_2 [31:0] Final 4 characters of IP core variation identifier string.

0x3034_3067

RO
0xB05 RX_PTP_CLK_PERIOD [19:0] clk_rxmac clock period.

Bits [19:16]: Full nanoseconds

Bits [15:0]: Fraction of a nanosecond

This value is set to the correct clock period for the required RX MAC clock frequency. RW
0xB06 RX_PTP_PMA_LATENCY [31:0] Latency through the RX PMA. This is the delay from the rx_serial pins to the RX PCS input.
  • Bits [31:16]: Full nanoseconds
  • Bits [15:0]: Fraction of a nanosecond

In Arria 10 devices, the RX PMA latency is 102.5 UI. One UI is approximately 38.8 ps.

Therefore, Intel recommends that you set this register to the value of 0x0003_FA1C . This is a device-dependent value that is sufficiently accurate in most cases. Intel recommends that you modify this value with extreme caution.

32'b0 RW

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