Low Latency 100-Gbps Ethernet IP Core User Guide

ID 683160
Date 4/15/2021
Document Table of Contents

1.4.1. Arria 10 Resource Utilization

Resource utilization changes depending on the parameter settings you specify in the LL 100GbE parameter editor. For example, if you turn on pause functionality or statistics counters in the LL 100GbE parameter editor, the IP core requires additional resources to implement the additional functionality.

Table 5.  IP Core FPGA Resource Utilization in Arria 10 Devices Lists the resources and expected performance for selected variations of the LL 100GbE IP core in an Arria 10 device.

These results were obtained using the Intel® Quartus® Prime software v16.1.

  • The numbers of ALMs and logic registers are rounded up to the nearest 100.
  • The numbers of ALMs, before rounding, are the ALMs needed numbers from the Intel® Quartus® Prime Fitter Report.

LL 100GbE Variation


Dedicated Logic Registers



LL 100GbE variation A

13000 22800 29

LL 100GbE variation B

22500 47100 73
LL 100GbE variation C 22700 47900 73

LL 100GbE variation D

29600 64500 109

CAUI-4 Variation


Dedicated Logic Registers



CAUI-4 variation B

24200 50800 77
CAUI-4 variation B with RS-FEC 54100 113200 143

Did you find the information on this page useful?

Characters remaining:

Feedback Message