Low Latency 100-Gbps Ethernet IP Core User Guide

ID 683160
Date 4/15/2021
Public
Document Table of Contents

3.2.8. External TX MAC PLL

If you turn on Use external TX MAC PLL in the LL 100GbE parameter editor, the IP core has an extra input port, clk_txmac_in, which drives the TX MAC clock. You must connect this input port to a clock source, usually a PLL on the device.

The port is expected to receive the clock from the external TX MAC PLL and drives the internal clock clk_txmac. The required TX MAC clock frequency is 390.625 MHz. User logic must drive clk_txmac_in from a PLL whose input is the PHY reference clock, clk_ref.

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