Low Latency 100-Gbps Ethernet IP Core User Guide

ID 683160
Date 4/15/2021
Public
Document Table of Contents

3.4.1.4. Pause Registers

The pause registers together with the pause signals implement the pause functionality defined in the IEEE 802.3ba-2010 High Speed Ethernet Standard. You can program the pause registers to control the insertion and decoding of pause frames, to help reduce traffic in congested networks.

Table 39.  TX Ethernet Flow Control (Pause Functionality) Registers Some registers are different depending on whether you select Standard flow control or Priority-based flow control in the LL 100GbE parameter editor. Where the difference is only whether the register refers to the single standard flow control priority class or whether distinct bits in the register refer to the individual priority queues, the two uses are documented together. In that case we understand that standard flow control effectively supports a single priority queue.
When your IP core implements priority-based flow control, the following registers provide an access window into an internal table of values, one per priority queue. The entry currently accessible in the registers is determined by the value you write to the TX_PAUSE_QNUMBER register.
  • RETRANSMIT_XOFF_HOLDOFF_QUANTA at offset 0x608
  • TX_PAUSE_QUANTA at offset 0x609

Addr

Name

Bit

Description

HW Reset Value

Access

0x600 TXSFC_REVID [31:0] TX standard flow control module revision ID. 0x0128_2014 RO
0x601 TXSFC_SCRATCH [31:0] Scratch register available for testing. 32'b0 RW
0x602 TXSFC_NAME_0 [31:0] First 4 characters of IP core variation identifier string. 0x7843_5352 RO
0x603 TXSFC_NAME_1 [31:0] Next 4 characters of IP core variation identifier string. 0x5054_5054 RO
0x604 TXSFC_NAME_2 [31:0] Final 4 characters of IP core variation identifier string. 0x3034_3067 RO
0x605 TX_PAUSE_EN [N-1:0] 7 Enable the IP core to transmit pause frames on the Ethernet link in response to a client request through the pause_insert_tx input signal or the TX_PAUSE_REQUEST register. If your IP core implements priority-based flow control, each bit of this field enables TX pause functionality for the corresponding priority queue.

Intel recommends that you signal a pause request using the pause_insert_tx signal rather than using the TX_PAUSE_REQUEST register.

N'b1 ...1 (1'b1 in each defined bit) RW
0x606 TX_PAUSE_REQUEST [N-1:0]7

Pause request. If bit [n] of the TX_PAUSE_EN register has the value of 1, setting bit [n] of the TX_PAUSE_REQUEST register field to the value of 1 triggers a XOFF pause packet insertion into the TX data stream on the Ethernet link. If the IP core implements priority-based flow control, the XOFF pause packet includes identity information for the corresponding priority queue.

If RETRANSMIT_XOFF_HOLDOFF_EN is turned on for the associated priority queue, as long as the value in TX_PAUSE_REQUEST bit [n] remains high, the IP core retransmits the XOFF pause packet at intervals determined by the retransmit hold-off value associated with this priority queue.

If bit [n] of the TX_PAUSE_EN register has the value of 1, resetting bit [n] of the TX_PAUSE_REQUEST register field to the value of 0 triggers an XON pause packet insertion into the TX data stream on the Ethernet link. If the IP core implements priority-based flow control, the XON pause packet includes identity information for the corresponding priority queue.

Other pause registers, described in this table, specify the properties of the pause packets.

Intel recommends that you signal a pause request using the pause_insert_tx signal rather than using the TX_PAUSE_REQUEST register.

0 RW
0x607 RETRANSMIT_XOFF_HOLDOFF_EN [N-1:0] 7 Enable XOFF pause frame retransmission hold-off functionality. If your IP core implements priority-based flow control with multiple priority queues, this register provides access to one bit for each priority queue.

Intel recommends that you maintain this register at the value of all ones.

If your IP core implements priority-based flow control, refer also to the description of the CFG_RETRANSMIT_HOLDOFF_EN and CFG_RETRANSMIT_HOLDOFF_QUANTA registers.

N'b1...1 (1'b1 in each defined bit) RW
0x608 RETRANSMIT_XOFF_HOLDOFF_QUANTA [15:0] Specifies hold-off time from XOFF pause frame transmission until retransmission, if retransmission hold-off functionality is enabled and pause request remains at the value of 1. If your IP core implements priority-based flow control with multiple priority queues, this register provides access to an internal table of retransmit-hold-off times, one for each priority queue. Accesses are indexed by the value in the TX_PAUSE_QNUMBER register.

Unit is quanta. One quanta is 512 bit times, which depends on the datapath width (512 bits) and the clk_txmac frequency. Note that in the case of 100GbE IP cores, one quanta is effectively one clk_txmac clock cycle.

Pause request can be either of the TX_PAUSE_REQUEST register pause request bit and the pause_insert_tx signal.

0xFFFF RW
0x609 TX_PAUSE_QUANTA [15:0] Specifies the pause time to be included in XOFF frames.

If your IP core implements priority-based flow control with multiple priority queues, this register provides access to an internal table of pause times, one for each priority queue. Accesses are indexed by the value in the TX_PAUSE_QNUMBER register.

Unit is quanta. One quanta is 512 bit times, which depends on the datapath width (512 bits) and the clk_txmac frequency. In 100GbE IP cores, a quanta is effectively a single clk_txmac clock cycle.

0xFFFF RW
0x60A if you set the value of Flow control mode to Standard flow control in the LL 100GbEparameter editor. TX_XOF_EN [0]

Enable the TX MAC to pause outgoing Ethernet traffic in response to a pause frame received on the RX Ethernet link and forwarded to the TX MAC by the RX MAC.

If the cfg_enable bit of the RX_PAUSE_ENABLE register has the value of 1, the RX MAC processes incoming pause frames. When the RX MAC processes an incoming pause frame with an address match, it notifies the TX MAC to pause outgoing traffic on the TX Ethernet link. The TX MAC pauses outgoing traffic on the TX Ethernet link in response to this notification only if bit [0] of the TX_XOF_EN register has the value of 1.

The value in the TX_XOF_EN register is only relevant when the cfg_enable bit of the RX_PAUSE_ENABLE register has the value of 1. If the cfg_enable bit of the RX_PAUSE_ENABLE register has the value of 0, pause frames received on the RX Ethernet link do not reach the TX MAC.

1'b0 RW
0x60A if you set the value of Flow control mode to Priority-based flow control in the LL 100GbEparameter editor. TX_PAUSE_QNUMBER [2:0] Queue number (index to internal table) of queue whose relevant values are currently accessible (readable and writeable) in these registers:
  • RETRANSMIT_XOFF_HOLDOFF_QUANTA at offset 0x608
  • TX_PAUSE_QUANTA at offset 0x609
0 RW
0x60B CFG_RETRANSMIT_HOLDOFF_EN [0] The CFG_RETRANSMIT_HOLDOFF_EN and CFG_RETRANSMIT_HOLDOFF_QUANTA registers provide a mechanism to specify a uniform retransmission hold-off delay for all priority queues. If CFG_RETRANSMIT_HOLDOFF_EN has the value of 1, the IP core enforces a retransmission hold-off delay for each priority queue that is the longer of the queue-specific retransmission hold-off delay accessible in the RETRANSMIT_XOFF_HOLDOFF_QUANTA register (if enabled) and the retransmission hold-off delay specified in the CFG_RETRANSMIT_HOLDOFF_QUANTA register.

CFG_RETRANSMIT_HOLDOFF_QUANTA unit is quanta. One quanta is 512 bit times, which depends on the datapath width (512 bits) and the clk_txmac frequency. In 100GbE IP cores, a quanta is effectively a single clk_txmac clock cycle.

These registers are present only if you set the value of Flow control mode to Priority-based flow control in the LL 100GbE parameter editor.

1'b0 RW
0x60C CFG_RETRANSMIT_HOLDOFF_QUANTA [15:0]
0x60D TX_PFC_DADDRL [31:0]

TX_PFC_DADDRH contains the 16 most significant bits of the destination address for PFC pause frames.

TX_PFC_DADDRL contains the 32 least significant bits of the destination address for PFC pause frames.

This feature allows you to program a destination address other than the standard multicast address for PFC frames, for debug or proprietary purposes.

{TX_PFC_DADDRH[15:0],TX_PFC_DADDRL[31:0]} can be a broadcast, multicast, or unicast address.

These registers are present only if you set the value of Flow control mode to Priority-based flow control in the LL 100GbE parameter editor.

0xC200_0001 RW
0x60E TX_PFC_DADDRH [15:0] 0x0180 RW
0x60F TX_PFC_SADDRL [31:0]

TX_PFC_SADDRH contains the 16 most significant bits of the source address for PFC pause frames.

TX_PFC_SADDRL contains the 32 least significant bits of the source address for PFC pause frames.

These registers are present only if you set the value of Flow control mode to Priority-based flow control in the LL 100GbE parameter editor.

0xCBFC_5ADD RW
0x610 TX_PFC_SADDRH [15:0] 0xE100 RW
Table 40.  RX Ethernet Flow Control (Pause Functionality) Registers Some registers are different depending on whether you select Standard flow control or Priority-based flow control in the LL 100GbE parameter editor. Where the difference is only whether the register refers to the single standard flow control priority class or whether distinct bits in the register refer to the individual priority queues, the two uses are documented together. In that case we understand that standard flow control effectively supports a single priority queue.

Addr

Name

Bit

Description

HW Reset Value

Access

0x700 RXSFC_REVID [31:0] RX standard flow control module revision ID. 0x0128_2014 RO
0x701 RXSFC_SCRATCH [31:0] Scratch register available for testing. 32'b0 RW
0x702 RXSFC_NAME_0 [31:0] First 4 characters of IP core variation identifier string. 0x7843_5352 RO
0x703 RXSFC_NAME_1 [31:0] Next 4 characters of IP core variation identifier string. 0x5054_5054 RO
0x704 RXSFC_NAME_2 [31:0] Final 4 characters of IP core variation identifier string. 0x3034_3067 RO

0x705

RX_PAUSE_ENABLE [N-1:0]

cfg_enable bits. When bit [n] has the value of 1, the RX MAC processes the incoming pause frames for priority class n whose address matches {DADDR1[31:0],DADDR0[15:0]}. When bit [n] has the value of 0, the RX MAC does not process any incoming pause frames for priority class n.

When the RX MAC processes an incoming pause frame with an address match, it notifies the TX MAC to pause outgoing traffic on the TX Ethernet link. If you implement priority-based flow control, the TX MAC pauses outgoing traffic from the indicated priority queue to the TX Ethernet link in response to this notification. If you implement standard flow control, the TX MAC pauses outgoing traffic on the TX Ethernet link in response to this notification only if bit [0] of the TX_XOF_EN register has the value of 1.

N'b1...1 (1'b1 in each defined bit) RW

0x706

RX_PAUSE_FWD [0] cfg_fwd_ctrl bit. When this bit has the value of 1, the RX MAC forwards matching pause frames to the RX client interface. When this bit has the value of 0, the RX MAC does not forward matching pause frames to the RX client interface. In both cases, the RX MAC forwards non-matching pause frames to the RX client interface. 1'b0 RW

0x707

RX_PAUSE_DADDRL

[31:0]

RX_PAUSE_DADDRL contains the 32 least significant bits of the destination address for pause frame matching.

RX_PAUSE_DADDRH contains the 16 most significant bits of the destination address for pause frame matching.

When pause frame processing is turned on, if {RX_PAUSE_DADDRH[15:0],RX_PAUSE_DADDRL[31:0]} matches the incoming pause frame destination address, the IP core processes the pause frame. if there is no match, the IP core does not process the pause frame.

{RX_PAUSE_DADDRH[15:0],RX_PAUSE_DADDRL[31:0]} can be a broadcast, multicast, or unicast address.

0xC200_0001

RW

0x708

RX_PAUSE_DADDRH

[15:0]

0x0180

RW

7 N is the number of priority queues. If the IP core implements Ethernet standard flow control, N is 1.

Did you find the information on this page useful?

Characters remaining:

Feedback Message