Low Latency 100-Gbps Ethernet IP Core User Guide

ID 683160
Date 4/15/2021
Public
Document Table of Contents

3.2.19. Clocks

You must set the transceiver reference clock (clk_ref) frequency to a value that the IP core supports. The LL 100GbE IP core supports clk_ref frequencies of 644.53125 MHz ±100 ppm and 322.265625 MHz ± 100 ppm. The ±100ppm value is required for any clock source providing the transceiver reference clock.

Sync–E IP core variations are IP core variations for which you turn on Enable SyncE in the parameter editor. These variations provide the RX recovered clock as a top-level output signal. This option is available only for IP core variations that target an Arria 10 device.

The Synchronous Ethernet standard, described in the ITU-T G.8261, G.8262, and G.8264 recommendations, requires that the TX clock be filtered to maintain synchronization with the RX reference clock through a sequence of nodes. The expected usage is that user logic drives the TX PLL reference clock with a filtered version of the RX recovered clock signal, to ensure the receive and transmit functions remain synchronized. In this usage model, a design component outside the LL 100GbE IP core performs the filtering.

Table 27.  Clock InputsDescribes the input clocks that you must provide.

Signal Name

Description

clk_status

Clocks the control and status interface. The clock quality and pin chosen are not critical. clk_status is expected to be a 100–125 MHz clock.

reconfig_clk

Clocks the Arria 10 transceiver reconfiguration interface. The clock quality and pin chosen are not critical. reconfig_clk is expected to be a 100 MHz clock; the allowed frequency range depends on Arria 10 transceiver requirements and is not IP core specific.

clk_ref

In IP core variations that target an Arria 10 device, clk_ref is the reference clock for the transceiver RX CDR PLL. In other IP core variations, clk_ref is the reference clock for the transceiver TX PLL and the RX CDR PLL.

The frequency of this input clock must match the value you specify for PHY reference frequency in the IP core parameter editor, with a ±100 ppm accuracy per the IEEE 802.3ba-2010 High Speed Ethernet Standard..

In addition, clk_ref must meet the jitter specification of the IEEE 802.3ba-2010 High Speed Ethernet Standard.

The PLL and clock generation logic use this reference clock to derive the transceiver and PCS clocks. The input clock should be a high quality signal on the appropriate dedicated clock pin. Refer to the relevant device datasheet for transceiver reference clock phase noise specifications.

clk_txmac_in If you turn on Use external TX MAC PLL in the LL 100GbE parameter editor, this clock drives the TX MAC. The port is expected to receive the clock from the external TX MAC PLL and drives the internal clock clk_txmac. The required TX MAC clock frequency is 390.625 MHz. User logic must drive clk_txmac_in from a PLL whose input is the PHY reference clock, clk_ref.

tx_serial_clk[9:0]

tx_serial_clk[3:0] (CAUI-4)

These input clocks are present only in variations that target an Arria 10 device. They are part of the external PLL interface to these variations. Each clock targets a single transceiver PHY link. You must drive these clocks from one or more TX transceiver PLLs that you configure separately from the LL 100GbE IP core.

Table 28.  Clock OutputsDescribes the output clocks that the IP core provides. In most cases these clocks participate in internal clocking of the IP core as well.

Signal Name

Description

clk_txmac

The TX clock for the IP core is clk_txmac. The TX MAC clock frequency is 390.625 MHz.

If you turn on Use external TX MAC PLL in the LL 100GbE parameter editor, the clk_txmac_in input clock drives clk_txmac.

clk_rxmac

The RX clock for the IP core is clk_rxmac. The RX MAC clock frequency is 390.625 MHz.

This clock is only reliable when rx_pcs_ready has the value of 1. The IP core generates clk_rxmac from a recovered clock that relies on the presence of incoming RX data.

clk_rx_recover RX recovered clock. This clock is available only if you turn on Enable SyncE in the LL 100GbE parameter editor.

The RX recovered clock frequency is 322.265625 MHz in standard variations and 402.83203 MHz in CAUI-4 variations..

The expected usage is that you drive the TX transceiver PLL reference clock with a filtered version of clk_rx_recover, to ensure the receive and transmit functions remain synchronized in your Synchronous Ethernet system. To do so you must instantiate an additional component in your design. The IP core does not provide filtering.

Figure 33. Clock Generation Circuitry Provides a high-level view of the clock generation circuitry and clock distribution to the transceiver. In Arria 10 variations, the TX transceiver PLL is configured outside the LL 100GbE IP core, and clk_ref drives the RX CDR PLL. In Arria 10 variations, you can connect a separate reference clock for the external TX transceiver PLL.

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