A.2. LL 100GbE IP Core User Guide Revision History
|Date||Compatible Intel® Quartus® Prime Version||Changes|
|2020.09.04||16.1||Added clarifying text for the tx_etstamp_ins_ctrl_offset_checksum_correction[15:0] signal in the 1588 PTP Interface Signals section: In a PTP packet, two bytes before the CRC field represent the valid offset for the checksum correction field.|
Clarified that this IP core is not supported in Platform Designer. Refer to Specifying the IP Core Parameters and Options.
Fixed assorted errors and minor typos.
Added link to KDB Answer that provides workaround for potential jitter on Arria 10 devices due to cascading ATX PLLs in the IP core. Refer to Handling Potential Jitter in Intel Arria 10 Devices.
Clarified that despite .vhd files being generated with the IP core, the IP core does not support VHDL. Refer to Files Generated for Arria 10 Variations.
Clarified that software must reset the PHY_SCLR_FRAME_ERROR register to the value of 0 within ten clk_status clock cycles of setting it to the value of 1. If you do not reset the PHY_SCLR_FRAME_ERROR register, the value in the PHY_FRAME_ERROR register is not useful. Refer to PHY Registers.
Clarified that the design example includes SDC files that you can modify for your own design. Refer to Compiling the Full Design and Programming the FPGA.
|2016.11.23||16.1||Initial version of Low Latency 100G Ethernet IP Core User Guide .
Changes from the 16.0 version of the Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide:
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