Low Latency 100-Gbps Ethernet IP Core User Guide

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ID 683160
Date 4/15/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the LL 100GbE IP Core 2. Getting Started 3. Functional Description 4. Debugging the Link A. Additional Information
1. About the LL 100GbE IP Core x
1.1. LL 100GbE IP Core Supported Features 1.2. IP Core Device Family and Speed Grade Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Release Information
1.2. IP Core Device Family and Speed Grade Support x
1.2.1. LL 100GbE IP Core Device Family Support 1.2.2. LL 100GbE IP Core Device Speed Grade Support
1.3. IP Core Verification x
1.3.1. Simulation Environment 1.3.2. Compilation Checking 1.3.3. Hardware Testing
1.4. Performance and Resource Utilization x
1.4.1. Arria 10 Resource Utilization 1.4.2. Stratix V Resource Utilization
2. Getting Started x
2.1. Installation and Licensing for LL 100GbE IP Core for Stratix® V Devices 2.2. Installing and Licensing Intel® FPGA IP Cores 2.3. Specifying the IP Core Parameters and Options 2.4. IP Core Parameters 2.5. Files Generated for Stratix V Variations 2.6. Files Generated for Arria 10 Variations 2.7. Integrating Your IP Core in Your Design 2.8. IP Core Testbenches 2.9. Compiling the Full Design and Programming the FPGA 2.10. Initializing the IP Core
2.2. Installing and Licensing Intel® FPGA IP Cores x
2.2.1. Intel® FPGA IP Evaluation Mode
2.7. Integrating Your IP Core in Your Design x
2.7.1. Pin Assignments 2.7.2. External Transceiver Reconfiguration Controller Required in Stratix V Designs 2.7.3. Transceiver PLL Required in Arria 10 Designs 2.7.4. Handling Potential Jitter in Intel® Arria® 10 Devices 2.7.5. External Time-of-Day Module for Variations with 1588 PTP Feature 2.7.6. External TX MAC PLL 2.7.7. Placement Settings for the LL 100GbE Core
2.8. IP Core Testbenches x
2.8.1. Testbench Behavior 2.8.2. Simulating the LL 100GbE IP Core With the Testbenches
2.8.2. Simulating the LL 100GbE IP Core With the Testbenches x
2.8.2.1. Generating the LL 100GbE Testbench 2.8.2.2. Optimizing the IP Core Simulation With the Testbenches 2.8.2.3. Simulating with the Modelsim Simulator 2.8.2.4. Simulating with the NCSim Simulator 2.8.2.5. Simulating with the VCS Simulator 2.8.2.6. Testbench Output Example
3. Functional Description x
3.1. High Level System Overview 3.2. LL 100GbE IP Core Functional Description 3.3. Signals 3.4. Software Interface: Registers 3.5. Ethernet Glossary
3.2. LL 100GbE IP Core Functional Description x
3.2.1. LL 100GbE IP Core TX Datapath 3.2.2. LL 100GbE IP Core TX Data Bus Interfaces 3.2.3. LL 100GbE IP Core RX Datapath 3.2.4. LL 100GbE IP Core RX Data Bus Interfaces 3.2.5. Low Latency 100GbE CAUI–4 PHY 3.2.6. External Reconfiguration Controller 3.2.7. External Transceiver PLL 3.2.8. External TX MAC PLL 3.2.9. Congestion and Flow Control Using Pause Frames 3.2.10. Pause Control and Generation Interface 3.2.11. Pause Control Frame Filtering 3.2.12. Link Fault Signaling Interface 3.2.13. Statistics Counters Interface 3.2.14. 1588 Precision Time Protocol Interfaces 3.2.15. PHY Status Interface 3.2.16. Transceiver PHY Serial Data Interface 3.2.17. Control and Status Interface 3.2.18. Arria 10 Transceiver Reconfiguration Interface 3.2.19. Clocks 3.2.20. Resets
3.2.1. LL 100GbE IP Core TX Datapath x
3.2.1.1. Preamble, Start, and SFD Insertion 3.2.1.2. Address Insertion 3.2.1.3. Length/Type Field Processing 3.2.1.4. Frame Padding 3.2.1.5. Frame Check Sequence (CRC-32) Insertion 3.2.1.6. Inter-Packet Gap Generation and Insertion 3.2.1.7. TX RSFEC 3.2.1.8. Error Insertion Test and Debug Feature
3.2.2. LL 100GbE IP Core TX Data Bus Interfaces x
3.2.2.1. LL 100GbE IP Core User Interface Data Bus 3.2.2.2. LL 100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface) 3.2.2.3. LL 100GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface) 3.2.2.4. Bus Quantization Effects With Adapters 3.2.2.5. User Interface to Ethernet Transmission
3.2.2.5. User Interface to Ethernet Transmission x
3.2.2.5.1. Order of Transmission
3.2.3. LL 100GbE IP Core RX Datapath x
3.2.3.1. LL 100GbE IP Core RX Filtering 3.2.3.2. LL 100GbE IP Core Preamble Processing 3.2.3.3. LL 100GbE IP Core FCS (CRC-32) Removal 3.2.3.4. LL 100GbE IP Core CRC Checking 3.2.3.5. LL 100GbE IP Core Malformed Packet Handling 3.2.3.6. RX CRC Forwarding 3.2.3.7. Inter-Packet Gap 3.2.3.8. RX RSFEC 3.2.3.9. Pause Ignore 3.2.3.10. Control Frame Identification
3.2.4. LL 100GbE IP Core RX Data Bus Interfaces x
3.2.4.1. LL 100GbE IP Core User Interface Data Bus 3.2.4.2. LL 100GbE IP Core RX Data Bus with Adapters (Avalon-ST Interface) 3.2.4.3. LL 100GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface)
3.2.9. Congestion and Flow Control Using Pause Frames x
3.2.9.1. Conditions Triggering XOFF Frame Transmission 3.2.9.2. Conditions Triggering XON Frame Transmission
3.2.13. Statistics Counters Interface x
3.2.13.1. OctetOK Count Interface
3.2.14. 1588 Precision Time Protocol Interfaces x
3.2.14.1. Implementing a 1588 System That Includes a LL 100GbE Core 3.2.14.2. PTP Receive Functionality 3.2.14.3. PTP Transmit Functionality 3.2.14.4. External Time-of-Day Module for 1588 PTP Variations 3.2.14.5. PTP Timestamp and TOD Formats 3.2.14.6. 1588 PTP Interface Signals
3.3. Signals x
3.3.1. LL 100GbE IP Core Signals
3.4. Software Interface: Registers x
3.4.1. LL 100GbE IP Core Registers 3.4.2. LL 100GbE Hardware Design Example Registers
3.4.1. LL 100GbE IP Core Registers x
3.4.1.1. PHY Registers 3.4.1.2. Link Fault Signaling Registers 3.4.1.3. LL 100GbE IP Core MAC Configuration Registers 3.4.1.4. Pause Registers 3.4.1.5. TX Statistics Registers 3.4.1.6. RX Statistics Registers 3.4.1.7. 1588 PTP Registers 3.4.1.8. TX Reed-Solomon FEC Registers 3.4.1.9. RX Reed-Solomon FEC Registers
3.4.2. LL 100GbE Hardware Design Example Registers x
3.4.2.1. Packet Client Registers
4. Debugging the Link x
4.1. Creating a Signal Tap Debug File to Match Your Design Hierarchy
A. Additional Information x
A.1. LL 100GbE IP Core User Guide Archives A.2. LL 100GbE IP Core User Guide Revision History
1. About the LL 100GbE IP Core
2. Getting Started
3. Functional Description
4. Debugging the Link
A. Additional Information

A.2. LL 100GbE IP Core User Guide Revision History

Date Compatible Intel® Quartus® Prime Version Changes
2021.04.15 16.1
  • Updated the descriptions for the following signals in Table: Signals of the 1588 Precision Time Protocol Interface:
    • tx_etstamp_ins_ctrl_residence_time_calc_format
    • tx_egress_timestamp_64b_data[63:0]
    • tx_egress_timestamp_96b_fingerprint[(W–1):0]
    • tx_egress_timestamp_64b_fingerprint[(W–1):0]
  • Clarified the description of PHY_PMA_SLOOP register.
2020.09.04 16.1 Added clarifying text for the tx_etstamp_ins_ctrl_offset_checksum_correction[15:0] signal in the 1588 PTP Interface Signals section: In a PTP packet, two bytes before the CRC field represent the valid offset for the checksum correction field.
2020.02.11 16.1
  • Updated for latest Intel branding standards.
  • Renamed Altera Debug Master Endpoint (ADME) to Native PHY Debug Master Endpoint (NPDME).
  • Added clarifying note for the tx_etstamp_ins_ctrl_residence_time_update signal in the PTP Transmit Functionality section.
  • Renamed OpenCore Plus IP Evaluation to Intel® FPGA IP Evaluation Mode and updated its content.
  • Fixed minor typos.
2018.01.03 16.1

Clarified that this IP core is not supported in Platform Designer. Refer to Specifying the IP Core Parameters and Options .

Fixed assorted errors and minor typos.

2017.11.06 16.1

Added link to KDB Answer that provides workaround for potential jitter on Arria 10 devices due to cascading ATX PLLs in the IP core. Refer to Handling Potential Jitter in Devices .

Clarified that despite .vhd files being generated with the IP core, the IP core does not support VHDL. Refer to Files Generated for Arria 10 Variations .

Added missing information: values of RX pause, TX pause, RX PTP, and TX PTP registers at offsets 0x02, 0x03, 0x04. Refer to Pause Registers and 1588 PTP Registers .

Clarified that software must reset the PHY_SCLR_FRAME_ERROR register to the value of 0 within ten clk_status clock cycles of setting it to the value of 1. If you do not reset the PHY_SCLR_FRAME_ERROR register, the value in the PHY_FRAME_ERROR register is not useful. Refer to PHY Registers.

Clarified that the design example includes SDC files that you can modify for your own design. Refer to Compiling the Full Design and Programming the FPGA.

2016.11.23 16.1 Initial version of Low Latency 100G Ethernet IP Core User Guide .

Changes from the 16.0 version of the Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide:

  • Updated for the Intel® Quartus® Prime software v16.1.
  • Removed information about the Low Latency 40GbE IP core. For the 16.1 release, the LL 40GbE IP core is documented in the 16.0 version of the Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide and changes are noted in the Intel FPGA IP Release Notes.
  • Added option for Reed-Solomon forward error correction (RS-FEC) in CAUI-4 variations. This new feature in the 16.1 software release adds a parameter and new registers to the IP core. Refer to IP Core Parameters , TX RSFEC, RX RSFEC, TX Reed-Solomon FEC Registers, and RX Reed-Solomon FEC Registers .
  • Updated for new handling of runt pause frames and pause frames with FCS errors. The IP core no longer processes these standard flow control pause frames. This feature is new in the 16.1 release and is relevant only for Arria 10 variations. Refer to Pause Control Frame Filtering.
  • Removed erroneous statement that the IP core ignores a Start control character it receives on any lane other than Lane 0. Refer to LL 100GbE IP Core Malformed Packet Handling.
  • Clarified that the IP core does not support a correct VHDL variation. You must generate a Verilog HDL variation of this IP core. Refer to Specifying the IP Core Parameters and Options .
  • Clarified that the control and status interface is a non-pipelined Avalon-MM interface with variable latency, and therefore cannot process multiple pending read transfers correctly. Refer to Control and Status Interface .
  • Clarified that the RX recovered clock frequency in CAUI-4 variations is 402.83203 MHz. Refer toClocks .
  • Clarified that the client is responsible to ensure that the PTP offset input values guarantee the full timestamp or checksum does not overflow the packet. The warning applies to tx_etstamp_ins_ctrl_offset_timestamp, tx_etstamp_ins_ctrl_offset_correction_field, tx_etstamp_ins_ctrl_offset_checksum_field, and tx_etstamp_ins_ctrl_offset_checksum_correction. Refer to 1588 PTP Interface Signals.
  • Clarified that the PHY_SCLR_FRAME_ERROR (at offset 0x324) and PHY_EIO_SFTRESET (at offset 0x325) registers are not self-clearing. Refer to PHY Registers.
  • Clarified the specific PLLs referred to in the descriptions of the PHY_TX_PLL_LOCKED register and the PHY_TX_COREPLL_LOCKED[1] register field. Refer to PHY Registers.
  • Clarified that SOP and EOP can occur on the RX client interface on the same clock cycle. Refer to IP Core RX Data Bus with Adapters (Avalon-ST Interface) and IP Core RX Data Bus Without Adapters (Custom Streaming Interface).
  • Reorganized the Getting Started chapter for clarity. Refer to Getting Started .
  • Relocated information about the PTP timestamp accuracy. Refer to 1588 Precision Time Protocol Interfaces.
  • Fixed assorted typos and minor errors.
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