Low Latency 100-Gbps Ethernet IP Core User Guide

ID 683160
Date 4/15/2021
Public
Document Table of Contents

3.2.15. PHY Status Interface

The rx_pcs_ready output signal is available to provide status information to user logic. This signal is asserted when the RX lanes are fully aligned and ready to receive data.

The tx_lanes_stable output signal is available to provide status information to user logic. This signal is asserted when the TX lanes are fully aligned and ready to transmit data.

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