Low Latency 100-Gbps Ethernet IP Core User Guide

ID 683160
Date 4/15/2021
Public
Document Table of Contents

3.4.1.3. LL 100GbE IP Core MAC Configuration Registers

The MAC configuration registers control the following MAC features in the RX and TX datapaths:

  • Fault link signaling on the Ethernet link (TX)
  • Local and remote fault status signals (RX)
  • CRC forwarding (RX)
  • Inter-packet gap IDLE removal (TX)
  • Maximum frame sizes for the CNTR_RX_OVERSIZE and CNTR_TX_OVERSIZE counters (RX and TX)

The fault link signaling and fault status signal registers are documented separately. Refer to Related Links below.

Table 37.  TX MAC Configuration Registers This table documents the non-fault link signaling registers in the TX MAC address space. The LINK_FAULT_CONFIG register at address 0x405 is documented with the link fault signaling registers. The LINK_FAULT_CONFIG register is available only if you turn on Enable link fault generation in the LL 100GbE parameter editor.

Address

Name

Bit

Description

HW Reset Value

Access

0x400 TXMAC_REVID [31:0] TX MAC revision ID. 0x02062015 RO
0x401 TXMAC_SCRATCH [31:0] Scratch register available for testing. 32'b0 RW
0x402 TXMAC_NAME_0 [31:0] First 4 characters of IP core variation identifier string "100gMACTxCSR". RO
0x403 TXMAC_NAME_1 [31:0] Next 4 characters of IP core variation identifier string "100gMACTxCSR". RO
0x404 TXMAC_NAME_2 [31:0] Final 4 characters of IP core variation identifier string "100gMACTxCSR". RO

0x406

IPG_COL_REM

[7:0]

Specifies the number of IDLE columns to be removed in every Alignment Marker period to compensate for alignment marker insertion. You can program this register to a larger value than the default value, for clock compensation.

This register is not present if you set the value of the Average interpacket gap parameter to Disable deficit idle counter in the LL 100GbE parameter editor.

20 (decimal) RW

0x407

MAX_TX_SIZE_CONFIG

[15:0]

Maximum size of Ethernet frames for CNTR_TX_OVERSIZE.

If the IP core transmits an Ethernet frame of size greater than the number of bytes specified in this register, and the IP core includes TX statistics registers, the IP core increments the 64-bit CNTR_TX_OVERSIZE register.

9600 (decimal)

RW

Table 38.  RX MAC Configuration Registers This table documents the non-fault link signaling registers in the RX MAC address space. The local and remote fault status register at address 0x508 is documented with the link fault signaling registers. The local and remote fault status register is available only if you turn on Enable link fault generation in the LL 100GbE parameter editor.

Address

Name

Bit

Description

HW Reset Value

Access

0x500 RXMAC_REVID [31:0] RX MAC revision ID. 0x02062015 RO
0x501 RXMAC_SCRATCH [31:0] Scratch register available for testing. 32'b0 RW
0x502 RXMAC_NAME_0 [31:0] First 4 characters of IP core variation identifier string "100gMACRxCSR". RO
0x503 RXMAC_NAME_1 [31:0] Next 4 characters of IP core variation identifier string "100gMACRxCSR". RO
0x504 RXMAC_NAME_2 [31:0] Final 4 characters of IP core variation identifier string "100gMACRxCSR". RO

0x506

MAX_RX_SIZE_CONFIG

[15:0]

Maximum size of Ethernet frames for CNTR_RX_OVERSIZE and for rx_error[3] or l<n>_rx_error[3] and for .the RxOctetsOK register.

If the IP core receives an Ethernet frame of size greater than the number of bytes specified in this register, and the IP core includes RX statistics registers, the IP core increments the 64-bit CNTR_RX_OVERSIZE register.

An Ethernet frame of size greater than the number of bytes specified in this register is considered oversized and therefore does not contribute to the value in the RxOctetsOK register.and does cause the assertion of rx_error[3] or l<n>_rx_error[3].

9600 (decimal)

RW

0x507

MAC_CRC_CONFIG

[0]

The RX CRC forwarding configuration register. Possible values are:

  • 1’b0: remove RX CRC— do not forward it to the RX client interface.
  • 1’b1: retain RX CRC—forward it to the RX client interface.

In either case, the IP core checks the incoming RX CRC and flags errors.

1’b0

RW

0x50A CFG_PLEN_CHECK [0] Enables payload length checking. If you set this bit to the value of 1, bit[4] of the rx_error signal flags any payload lengths that do not match the length field. 1'b1 RW

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