Low Latency 100-Gbps Ethernet IP Core User Guide

ID 683160
Date 4/15/2021
Public
Download
Document Table of Contents

1.4.2. Stratix V Resource Utilization

Resource utilization changes depending on the parameter settings you specify in the LL 100GbE parameter editor. For example, if you turn on pause functionality or statistics counters in the LL 100GbE parameter editor, the IP core requires additional resources to implement the additional functionality.

Table 6.  IP Core FPGA Resource Utilization in Stratix V Devices Lists the resources and expected performance for selected variations of the LL 100GbE IP core in a Stratix V device.

These results were obtained using the Quartus II software v14.1.

Note: Please note that at the time of publication, the LL 100GbE IP core that targets a Stratix V device has not been updated since the version compatible with the Intel® Quartus® Prime Standard Edition software v16.0.
  • The numbers of ALMs and logic registers are rounded up to the nearest 100.
  • The numbers of ALMs, before rounding, are the ALMs needed numbers from the Intel® Quartus® Prime Fitter Report.

100GbE Variation

ALMs

Dedicated Logic Registers

Memory

M20K

100GbE variation A

9500 23000 29

100GbE variation B

20900 48400 61
100GbE variation C 22100 52500 61

100GbE variation D

26900 63700 65

Did you find the information on this page useful?

Characters remaining:

Feedback Message