Low Latency 100-Gbps Ethernet IP Core User Guide

ID 683160
Date 4/15/2021
Public
Document Table of Contents

2.3. Specifying the IP Core Parameters and Options

The LL 100GbE parameter editor allows you to quickly configure your custom IP variation. Use the following steps to specify IP core options and parameters in the Quartus Prime software.
  1. In the IP Catalog (Tools > IP Catalog), select a target device family. The LL 100GbE IP core is not supported in Platform Designer (Standard).
  2. In the IP Catalog, locate and double-click the name of the IP core to customize (Low Latency 100G Ethernet ). The New IP Variation window appears.
  3. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file with one of the following names:
    • <your_ip> .qsys (for Arria 10 variations generated in the Intel® Quartus® Prime Standard Edition software)
    • <your_ip> .ip (for Arria 10 variations generated in the Intel® Quartus® Prime Pro Edition software)
    • <your_ip> .qip (for Stratix V variations)
  4. If your IP core targets the Arria 10 device family, you must select a specific device in the Device field or maintain the default device the Quartus Prime software lists. If you target a specific Intel development kit, the hardware design example overwrites the selection with the device on the target board.
  5. Click OK. The parameter editor appears.
  6. Specify the parameters and options for your IP variation in the parameter editor, including one or more of the following. Refer to your IP core user guide for information about specific IP core parameters.
    • Specify parameters defining the IP core functionality, port configurations, and device-specific features.
    • Specify options for processing the IP core files in other EDA tools.
    • A functional VHDL IP core is not available. Specify Verilog HDL only, for your IP core variation.
  7. For Arria 10 variations, follow these steps:
    1. Optionally, to generate a simulation testbench or example project, follow the instructions in Generating the LL 100GbE Testbench.
    2. Click Generate HDL. The Generation dialog box appears.
    3. Specify output file generation options, and then click Generate. The IP variation files generate according to your specifications.
    4. Click Finish. The parameter editor adds the top-level .qsys file to the current project automatically. If you are prompted to manually add the .qsys or .ip file to the project, click Project > Add/Remove Files in Project to add the file.
  8. For Stratix V variations, follow these steps:
    1. Click Finish.
    2. Optionally, to generate a simulation testbench or example project, follow the instructions in Generating the LL 100GbE Testbench.
      After you click Finish and optionally follow the additional step to generate a simulation testbench and example project, if available for your IP core variation, the parameter editor adds the top-level .qip file to the current project automatically. If you are prompted to manually add this file to the project, click Project > Add/Remove Files in Project to add the file.
  9. After generating and instantiating your IP variation, make appropriate pin assignments to connect ports.

Did you find the information on this page useful?

Characters remaining:

Feedback Message