Low Latency 100-Gbps Ethernet IP Core User Guide

ID 683160
Date 4/15/2021
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3.2.2.3. LL 100GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface)

Figure 13. TX Client to MAC Interface Without Adapters
Table 17.  Signals of the Custom Streaming TX Client InterfaceAll interface signals are clocked by the clk_txmac clock.

Signal Name

Direction

Description

din[255:0]

Input

Data bytes to send in big-endian mode.

Most significant 64-bit word is in the higher-order bits: bits [255:192]

The LL 100GbE IP core does not process incoming frames of less than nine bytes correctly. You must ensure such frames do not reach the TX client interface.

din_sop[3:0]

Input

Start of packet (SOP) location in the TX data bus. Only the most significant byte of each 64‑bit word may be a start of packet. Bits 255, 191, 127, and 63 are allowed locations.

Bit 0 of din_sop corresponds to the data word in din[63:0].

din_eop[3:0]

Input

End of packet location in the TX data bus. Indicates the 64-bit word that holds the end-of-packet byte. Any byte may be the last byte in a packet.

Bit 0 of din_eop corresponds to the data word in din[63:0].

din_eop_empty[11:0]

Input

Indicates the number of empty (invalid) bytes in the end-of-packet 8-byte word indicated by din_eop.

If din_eop[z] has the value of 0, then the value of din_eop_empty[(z+2):z] does not matter. However, if din_eop[z] has the value of 1, then you must set the value of din_eop_empty[(z+2):z] to the number of empty (invalid) bytes in the end-of-packet word z.

For example, if you have a LL 100GbE IP core and want to indicate that in the current clk_txmac clock cycle, byte 6 in word 2 of din is an end-of-packet byte, and no other words hold an end-of-packet byte in the current clock cycle, you must set the value of din_eop to 4'b0100 and the value of din_eop_empty to 12'b000_110_000_000.

din_idle[3:0]

Input

Indicates the words in din that hold Idle bytes or control information rather than Ethernet data. One-hot encoded.

din_req

Output

Indicates that input data was accepted by the IP core.

tx_error[3:0] Input When asserted in an EOP cycle (while din_eop is non-zero), directs the IP core to insert an error in the corresponding packet before sending it on the Ethernet link.

This signal is a test and debug feature. In loopback mode, the IP core recognizes the packet upon return as a malformed packet.

clk_txmac

Output

TX MAC clock. The clock frequency should be 390.625 MHz. The clk_txmac clock and the clk_rxmac clock (which clocks the RX datapath) are assumed to have the same frequency.

The IP core reads the bytes in big endian order. A packet may start in the most significant byte of any word. A packet may end on any byte.

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