Low Latency 100-Gbps Ethernet IP Core User Guide

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ID 683160
Date 4/15/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the LL 100GbE IP Core 2. Getting Started 3. Functional Description 4. Debugging the Link A. Additional Information
1. About the LL 100GbE IP Core x
1.1. LL 100GbE IP Core Supported Features 1.2. IP Core Device Family and Speed Grade Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Release Information
1.2. IP Core Device Family and Speed Grade Support x
1.2.1. LL 100GbE IP Core Device Family Support 1.2.2. LL 100GbE IP Core Device Speed Grade Support
1.3. IP Core Verification x
1.3.1. Simulation Environment 1.3.2. Compilation Checking 1.3.3. Hardware Testing
1.4. Performance and Resource Utilization x
1.4.1. Arria 10 Resource Utilization 1.4.2. Stratix V Resource Utilization
2. Getting Started x
2.1. Installation and Licensing for LL 100GbE IP Core for Stratix® V Devices 2.2. Installing and Licensing Intel® FPGA IP Cores 2.3. Specifying the IP Core Parameters and Options 2.4. IP Core Parameters 2.5. Files Generated for Stratix V Variations 2.6. Files Generated for Arria 10 Variations 2.7. Integrating Your IP Core in Your Design 2.8. IP Core Testbenches 2.9. Compiling the Full Design and Programming the FPGA 2.10. Initializing the IP Core
2.2. Installing and Licensing Intel® FPGA IP Cores x
2.2.1. Intel® FPGA IP Evaluation Mode
2.7. Integrating Your IP Core in Your Design x
2.7.1. Pin Assignments 2.7.2. External Transceiver Reconfiguration Controller Required in Stratix V Designs 2.7.3. Transceiver PLL Required in Arria 10 Designs 2.7.4. Handling Potential Jitter in Intel® Arria® 10 Devices 2.7.5. External Time-of-Day Module for Variations with 1588 PTP Feature 2.7.6. External TX MAC PLL 2.7.7. Placement Settings for the LL 100GbE Core
2.8. IP Core Testbenches x
2.8.1. Testbench Behavior 2.8.2. Simulating the LL 100GbE IP Core With the Testbenches
2.8.2. Simulating the LL 100GbE IP Core With the Testbenches x
2.8.2.1. Generating the LL 100GbE Testbench 2.8.2.2. Optimizing the IP Core Simulation With the Testbenches 2.8.2.3. Simulating with the Modelsim Simulator 2.8.2.4. Simulating with the NCSim Simulator 2.8.2.5. Simulating with the VCS Simulator 2.8.2.6. Testbench Output Example
3. Functional Description x
3.1. High Level System Overview 3.2. LL 100GbE IP Core Functional Description 3.3. Signals 3.4. Software Interface: Registers 3.5. Ethernet Glossary
3.2. LL 100GbE IP Core Functional Description x
3.2.1. LL 100GbE IP Core TX Datapath 3.2.2. LL 100GbE IP Core TX Data Bus Interfaces 3.2.3. LL 100GbE IP Core RX Datapath 3.2.4. LL 100GbE IP Core RX Data Bus Interfaces 3.2.5. Low Latency 100GbE CAUI–4 PHY 3.2.6. External Reconfiguration Controller 3.2.7. External Transceiver PLL 3.2.8. External TX MAC PLL 3.2.9. Congestion and Flow Control Using Pause Frames 3.2.10. Pause Control and Generation Interface 3.2.11. Pause Control Frame Filtering 3.2.12. Link Fault Signaling Interface 3.2.13. Statistics Counters Interface 3.2.14. 1588 Precision Time Protocol Interfaces 3.2.15. PHY Status Interface 3.2.16. Transceiver PHY Serial Data Interface 3.2.17. Control and Status Interface 3.2.18. Arria 10 Transceiver Reconfiguration Interface 3.2.19. Clocks 3.2.20. Resets
3.2.1. LL 100GbE IP Core TX Datapath x
3.2.1.1. Preamble, Start, and SFD Insertion 3.2.1.2. Address Insertion 3.2.1.3. Length/Type Field Processing 3.2.1.4. Frame Padding 3.2.1.5. Frame Check Sequence (CRC-32) Insertion 3.2.1.6. Inter-Packet Gap Generation and Insertion 3.2.1.7. TX RSFEC 3.2.1.8. Error Insertion Test and Debug Feature
3.2.2. LL 100GbE IP Core TX Data Bus Interfaces x
3.2.2.1. LL 100GbE IP Core User Interface Data Bus 3.2.2.2. LL 100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface) 3.2.2.3. LL 100GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface) 3.2.2.4. Bus Quantization Effects With Adapters 3.2.2.5. User Interface to Ethernet Transmission
3.2.2.5. User Interface to Ethernet Transmission x
3.2.2.5.1. Order of Transmission
3.2.3. LL 100GbE IP Core RX Datapath x
3.2.3.1. LL 100GbE IP Core RX Filtering 3.2.3.2. LL 100GbE IP Core Preamble Processing 3.2.3.3. LL 100GbE IP Core FCS (CRC-32) Removal 3.2.3.4. LL 100GbE IP Core CRC Checking 3.2.3.5. LL 100GbE IP Core Malformed Packet Handling 3.2.3.6. RX CRC Forwarding 3.2.3.7. Inter-Packet Gap 3.2.3.8. RX RSFEC 3.2.3.9. Pause Ignore 3.2.3.10. Control Frame Identification
3.2.4. LL 100GbE IP Core RX Data Bus Interfaces x
3.2.4.1. LL 100GbE IP Core User Interface Data Bus 3.2.4.2. LL 100GbE IP Core RX Data Bus with Adapters (Avalon-ST Interface) 3.2.4.3. LL 100GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface)
3.2.9. Congestion and Flow Control Using Pause Frames x
3.2.9.1. Conditions Triggering XOFF Frame Transmission 3.2.9.2. Conditions Triggering XON Frame Transmission
3.2.13. Statistics Counters Interface x
3.2.13.1. OctetOK Count Interface
3.2.14. 1588 Precision Time Protocol Interfaces x
3.2.14.1. Implementing a 1588 System That Includes a LL 100GbE Core 3.2.14.2. PTP Receive Functionality 3.2.14.3. PTP Transmit Functionality 3.2.14.4. External Time-of-Day Module for 1588 PTP Variations 3.2.14.5. PTP Timestamp and TOD Formats 3.2.14.6. 1588 PTP Interface Signals
3.3. Signals x
3.3.1. LL 100GbE IP Core Signals
3.4. Software Interface: Registers x
3.4.1. LL 100GbE IP Core Registers 3.4.2. LL 100GbE Hardware Design Example Registers
3.4.1. LL 100GbE IP Core Registers x
3.4.1.1. PHY Registers 3.4.1.2. Link Fault Signaling Registers 3.4.1.3. LL 100GbE IP Core MAC Configuration Registers 3.4.1.4. Pause Registers 3.4.1.5. TX Statistics Registers 3.4.1.6. RX Statistics Registers 3.4.1.7. 1588 PTP Registers 3.4.1.8. TX Reed-Solomon FEC Registers 3.4.1.9. RX Reed-Solomon FEC Registers
3.4.2. LL 100GbE Hardware Design Example Registers x
3.4.2.1. Packet Client Registers
4. Debugging the Link x
4.1. Creating a Signal Tap Debug File to Match Your Design Hierarchy
A. Additional Information x
A.1. LL 100GbE IP Core User Guide Archives A.2. LL 100GbE IP Core User Guide Revision History
1. About the LL 100GbE IP Core
2. Getting Started
3. Functional Description
4. Debugging the Link
A. Additional Information

3.4.1.1. PHY Registers

Table 34.  PHY Registers

Addr

Name

Bit

Description

HW Reset Value

Access

0x300 PHY_REVID [31:0] IP core PHY module revision ID. 0x02062015 RO
0x301 PHY_SCRATCH [31:0] Scratch register available for testing. 32'b0 RW
0x302 PHY_NAME_0 [31:0] First 4 characters of IP core variation identifier string "100GE pcs ". RO
0x303 PHY_NAME_1 [31:0] Next 4 characters of IP core variation identifier string "100GE pcs ". RO
0x304 PHY_NAME_2 [31:0] Final 4 characters of IP core variation identifier string "100GE pcs ". RO
0x310 PHY_CONFIG [5] set_data_lock: Directs the PLL to lock to data. 6'b0 RW
[4] set_ref_lock: Directs the PLL to lock to the reference clock.
[3] rxp_ignore_freq: Directs the IP core to proceed with the internal reset sequence (to reset the RX PLL) without waiting for the RX CDR PLL to lock.
[2] soft_rxp_rst: RX PLL soft reset
[1] soft_txp_rst: TX PLL soft reset
[0] eio_sys_rst: PMA system reset. Set this bit to start the internal reset sequence.

0x313

PHY_PMA_SLOOP

[3:0] or [9:0]

Serial PMA loopback. Each bit that is asserted directs the IP core to connect the corresponding TX–RX lane pair on the internal loopback path, by setting the corresponding transceiver in serial loopback mode.

This option is not available for CAUI-4 variations.

0 RW

0x314

PHY_PCS_INDIRECT_ADDR

[2:0]

Supports indirect addressing of individual FIFO flags in the 10G PCS Native PHY IP core. Program this register with the encoding for a specific FIFO flag. The flag values (one per transceiver) are then accessible in the PHY_PCS_INDIRECT_DATA register.

The value in the PHY_PCS_INDIRECT_ADDR register directs the IP core to make available the following FIFO flag:

  • 3'b111: RX partial empty
  • 3'b110: RX partial full
  • 3'b101: RX empty
  • 3'b100: RX full
  • 3'b011: TX partial empty
  • 3'b010: TX partial full
  • 3'b001: TX empty
  • 3'b000: TX full
3'b0 RW

0x315

PHY_PCS_INDIRECT_DATA

[3:0] or [9:0]

PCS indirect data. To read a FIFO flag, set the value in the PHY_PCS_INDIRECT_ADDR register to indicate the flag you want to read. After you set the specific flag indication in the PHY_PCS_INDIRECT_ADDR register, each bit [n] in the PHY_PCS_INDIRECT_DATA register has the value of that FIFO flag for the transceiver channel for lane [n].

This register has ten valid bits [9:0] in standard LL 100GbE IP core variations. This register is not valid for CAUI-4 variations.

TX full flags RO

0x320

PHY_TX_PLL_LOCKED

[9:0]

Each bit that is asserted indicates that the corresponding lane TX transceiver PLL is locked. 10'b0 RO

0x321

PHY_EIOFREQ_LOCKED

[9:0]

Each bit that is asserted indicates that the corresponding lane RX CDR PLL is locked.

10'b0

RO

RO

0x322

PHY_TX_COREPLL_LOCKED

[2] RX PLL is locked. 3'b0

RO

[1] TX MAC PLL is locked.
[0] TX PCS is ready.

0x323

PHY_FRAME_ERROR

[3:0] or [19:0]

Each bit that is asserted indicates that the corresponding virtual lane has a frame error. If you read a non-zero value in this register, the virtual lanes that correspond to non-zero bits have observed frame errors.

You can clear these bits with the PHY_SCLR_FRAME_ERROR register.

Intel recommends that you set bit [0] of the PHY_SCLR_FRAME_ERROR register and read the PHY_FRAME_ERROR register again to determine if the PHY frame error is generated continuously.

These bits are not sticky: the IP core clears them more than once while attempting to achieve alignment.

0xF or 0xFFFFF

RO

0x324

PHY_SCLR_FRAME_ERROR

[0]

Synchronous clear for PHY_FRAME_ERROR register. Write the value of 1 to this register to clear the PHY_FRAME_ERROR register. This bit is not self-clearing. You should reset this register to the value of 0 within ten clk_status clock cycles. If you do not reset the PHY_SCLR_FRAME_ERROR register, the value in the PHY_FRAME_ERROR register is not useful.

1'b0

RW

0x325 PHY_EIO_SFTRESET [1] Set this bit to clear the RX FIFO. This bit is not self-clearing. 2'b00 RW
[0] RX PCS reset: set this bit to reset the RX PCS. This bit is not self-clearing.

0x326

PHY_RXPCS_STATUS

[1:0] Indicates the RX PCS is fully aligned and ready to accept traffic.
  • Bit [1]: HI BER status (bit error rate is high according to Ethernet standard definition). This bit maintains the value of 1'b0 unless you turn on Enable link fault generation .
  • Bit [0]: RX PCS fully aligned status.
0 RO

0x340

PHY_REFCLK_KHZ

[31:0] Reference clock frequency in KHz, assuming the clk_status clock has the frequency of 100 MHz. The reference clock frequency is the value in the PHY_REFCLK_KHZ register times the frequency of the clk_status clock, divided by 100. RO

0x341

PHY_RXCLK_KHZ

[31:0] RX clock (clk_rxmac) frequency in KHz, assuming the clk_status clock has the frequency of 100 MHz. The RX clock frequency is the value in the PHY_RXCLK_KHZ register times the frequency of the clk_status clock, divided by 100. RO

0x342

PHY_TXCLK_KHZ

[31:0] TX clock (clk_txmac) frequency in KHz, assuming the clk_status clock has the frequency of 100 MHz. The TX clock frequency is the value in the PHY_TXCLK_KHZ register times the frequency of the clk_status clock, divided by 100. RO

0x343

PHY_RECCLK_KHZ

[31:0] RX recovered clock frequency in KHz, assuming the clk_status clock has the frequency of 100 MHz. The RX recovered clock frequency is the value in the PHY_RECCLK_KHZ register times the frequency of the clk_status clock, divided by 100. RO

0x344

PHY_TXIOCLK_KHZ

[31:0] TX PMA clock frequency in KHz, assuming the clk_status clock has the frequency of 100 MHz. The TX PMA clock frequency is the value in the PHY_TX10CLK_KHZ register times the frequency of the clk_status clock, divided by 100. RO
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