1. About the 25G Ethernet Intel FPGA IP 2. Getting Started 3. 25G Ethernet Intel FPGA IP Parameters 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Debugging the Link 9. 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide Archives 10. Document Revision History for the 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers 6.4. Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. PHY Interface Signals 6.7. 1588 PTP Interface Signals 6.8. Miscellaneous Status and Debug Signals 6.9. Reset Signals
The transceivers require a separately instantiated advanced transmit (ATX) PLL to generate the high speed serial clock. In many cases, the same ATX PLL can serve as input to an additional transceiver that has similar input clocking requirements. In comparison to the fractional PLL (fPLL) and clock multiplier unit PLL, the ATX PLL has the best jitter performance and supports the highest frequency operation.
|tx_serial||Output||TX transceiver signal. Each tx_serial bit becomes two physical pins that form a differential pair.|
|rx_serial||Input||RX transceiver signals. Each rx_serial bit becomes two physical pins that form a differential pair.|
|clk_ref||Input||The PLL reference clock. Input to the clock data recovery (CDR) circuitry in the RX PMA. The frequency of this clock is 644.53125 MHz or 322.265625 MHz.|
|tx_serial_clk||Input||High speed serial clock driven by the ATX PLL. The frequency of this clock is 12.890625 GHz.|
|tx_serial_clk0||Input||High speed serial clock driven by the ATX PLL for 25G data rate. The frequency of this clock is 12.890625 GHz.|
|tx_serial_clk1||Input||High speed serial clock driven by the ATX PLL for 10G data rate. The frequency of this clock is 5.15625 GHz.|
|tx_pll_locked||Input||Lock signal from ATX PLL. Indicates all ATX PLL(s) are locked.|
- The integrated transceivers supports adaptation mode by setting the RX PMA Adaptation Mode parameter in the internal generated transceiver IP to Adaptive CTLE, Adaptive VGA, All-Tap Adaptive DFE mode. Refer to the Analog PMA Settings Parameters and RX PMA Use Model sections of the L- and H-Tile Transceiver PHY User Guide for more information.
- Intel® Stratix® 10 devices use the OSC_CLK_1 pin to provide the transceiver calibration clock source. You must provide a 25, 100, or 125 MHz free running and stable clock to OSC_CLK_1. The FPGA's Internal Oscillator cannot be used for transceiver calibration. Do not select this clock source as the Configuration clock source in the Intel® Quartus® Prime settings. For more information, refer to the Calibration section of the L- and H-Tile Transceiver PHY User Guide.
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