Visible to Intel only — GUID: lbl1457460425907
Ixiasoft
Visible to Intel only — GUID: lbl1457460425907
Ixiasoft
6.9. Reset Signals
Signal |
Direction |
Description |
---|---|---|
tx_rst_n | Input | Active low hard reset signal. Resets the TX interface, including the TX PCS and TX MAC. This reset leads to the deassertion of the tx_lanes_stable output signal. |
rx_rst_n | Input | Active low hard reset signal. Resets the RX interface, including the RX PCS and RX MAC. This reset leads to the deassertion of the rx_pcs_ready output signal. |
csr_rst_n | Input | Active low hard global reset. Resets the full IP core. Resets the TX MAC, RX MAC, TX PCS, RX PCS, adapters, transceivers, and control, status, and statistic registers. This reset leads to the deassertion of the tx_lanes_stable and rx_pcs_ready output signals. |
channel_reset | Input | This port is only present if the Enable 10G/25G Dynamic Rate Switching parameter is enabled. Before initiating reconfiguration between speeds, assert this signal to hold the TX or RX data paths in reset. |
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