25G Ethernet Intel® Stratix® 10 FPGA IP User Guide

ID 683154
Date 9/15/2021
Public
Document Table of Contents

1.5. Performance and Resource Utilization

The following table shows the typical device resource utilization for selected configurations using the current version of the Intel® Quartus® Prime software. With the exception of M20K memory blocks, the numbers of ALMs and logic registers are rounded up to the nearest 100. The timing margin for this IP core is a minimum of 15%.

Table 5.  IP Core Variation Encoding for Resource Utilization Table for MAC+PCS+PMA Core Variant"On" indicates the parameter is turned on. The symbol "—" indicates the parameter is turned off or not available.
IP Core Variation A B C D
Parameter
Ready Latency 0 0 3 3
Enable RS-FEC On
Core Variant MAC+PCS+PMA
Enable flow control Standard flow control, 1 queue Standard flow control, 1 queue Standard flow control, 1 queue
Enable link fault generation On On
Enable preamble passthrough On On
Enable TX CRC passthrough On
Enable MAC statistics counters On On On
Enable IEEE 1588 On
Enable 10G/25G Dynamic Rate Switching On
Enable Native PHY Debug Master Endpoint (NPDME) On
Table 6.  IP Core FPGA Resource Utilization for 25G Ethernet Intel FPGA IP Core with MAC+PCS+PMA Core Variant for Intel® Stratix® 10 DevicesLists the resources and expected performance for selected variations of the 25G Ethernet Intel FPGA IP core.

These results were obtained using the Intel® Quartus® Prime software v20.1.

  • The transceiver PLL reference clock frequency is 644.531250 MHz.
  • The numbers of ALMs and logic registers are rounded up to the nearest 100.
  • The numbers of ALMs, before rounding, are the ALMs needed numbers from the Intel® Quartus® Prime Fitter Report.

IP Core Variation

ALMs

Dedicated Logic Registers

Block Memory Bits

A 4300 9200 0
B 17700 45200 114880
C 14700 38400 11912
D 8700 18700 1024
Table 7.  IP Core Round Trip LatencyThe round trip latency values are based on the following definitions and assumptions:
  • Round trip latency is measured as the time taken for a packet to travel from TX Avalon® streaming interface to the RX Avalon® streaming interface with the IP core in serial loopback mode.
  • Latency values are obtained via simulation of the IP Core's example design generated using Intel® Quartus® Prime software v20.1. These values are expected to be different across different builds.
  • Synopsys's VCS simulator is used when measuring the following values. These values may differ across different simulators.

IP Core Variation

Latency (ns)

A 210.0
B 1002.2
C 465.2
D 10G: 668.8

25G: 265.5

Table 8.  IP Core Variation Encoding for Resource Utilization Table for MAC+PCS Core Variant"On" indicates the parameter is turned on. The symbol "—" indicates the parameter is turned off or not available.
IP Core Variation A B C D
Parameter
Ready Latency 0 0 3 3
Enable RS-FEC On
Core Variant MAC+PCS
Enable flow control Standard flow control, 1 queue Standard flow control, 1 queue Standard flow control, 1 queue
Enable link fault generation On On
Enable preamble passthrough On On
Enable TX CRC passthrough On
Enable MAC statistics counters On On On
Enable IEEE 1588 On
Enable 10G/25G Dynamic Rate Switching On
Enable Native PHY Debug Master Endpoint (NPDME) On
Table 9.  IP Core FPGA Resource Utilization for 25G Ethernet Intel FPGA IP Core with MAC+PCS Core Variant for Intel® Stratix® 10 DevicesLists the resources and expected performance for selected variations of the 25G Ethernet Intel FPGA IP core.

These results were obtained using the Intel® Quartus® Prime software v20.1.

  • The transceiver PLL reference clock frequency is 644.531250 MHz.
  • The numbers of ALMs and logic registers are rounded up to the nearest 100.
  • The numbers of ALMs, before rounding, are the ALMs needed numbers from the Intel® Quartus® Prime Fitter Report.

IP Core Variation

ALMs

Dedicated Logic Registers

Block Memory Bits

A 4300 9200 0
B 17700 45600 114880
C 14600 37800 11912
D 8600 19500 1024

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