25G Ethernet Intel® Stratix® 10 FPGA IP User Guide

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ID 683154
Date 9/15/2021
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Document Table of Contents
Document Table of Contents x
1. About the 25G Ethernet Intel FPGA IP 2. Getting Started 3. 25G Ethernet Intel FPGA IP Parameters 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Debugging the Link 9. 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide Archives 10. Document Revision History for the 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide
1. About the 25G Ethernet Intel FPGA IP x
1.1. Release Information 1.2. Features 1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support 1.4. IP Core Verification 1.5. Performance and Resource Utilization
1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support x
1.3.1. 25G Ethernet Intel FPGA IP Core Device Family Support 1.3.2. 25G Ethernet Intel FPGA IP Core Device Speed Grade Support
1.4. IP Core Verification x
1.4.1. Simulation Environment 1.4.2. Compilation Checking 1.4.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the Intel® Stratix® 10 IP Core Parameters and Options 2.3. Simulating the IP Core 2.4. Generated File Structure 2.5. Integrating Your IP Core in Your Design 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Adding the External Time-of-Day Module for Variations with 1588 PTP Feature 2.5.4. Placement Settings for the 25G Ethernet Intel FPGA IP Core
4. Functional Description x
4.1. 25G Ethernet Intel FPGA IP Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. 25G Ethernet Intel FPGA IP Core Functional Description x
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath 4.1.2. 25 GbE TX PCS 4.1.3. TX RS-FEC 4.1.4. 25G Ethernet Intel FPGA IP Core RX MAC Datapath 4.1.5. Link Fault Signaling Interface 4.1.6. 25 GbE RX PCS 4.1.7. RX RS-FEC 4.1.8. Flow Control 4.1.9. 1588 Precision Time Protocol Interfaces
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion 4.1.1.4. Frame Check Sequence (CRC32) Insertion
4.1.4. 25G Ethernet Intel FPGA IP Core RX MAC Datapath x
4.1.4.1. IP Core Preamble Processing 4.1.4.2. IP Core Malformed Packet Handling 4.1.4.3. Length/Type Field Processing 4.1.4.4. RX CRC Checking and Dynamic Forwarding
4.1.4.3. Length/Type Field Processing x
4.1.4.3.1. Length Checking
4.1.8. Flow Control x
4.1.8.1. TX Pause/PFC Flow Control Frame Transmission Request 4.1.8.2. XON/XOFF Pause Frames
4.1.9. 1588 Precision Time Protocol Interfaces x
4.1.9.1. Implementing a 1588 System That Includes a 25G Ethernet Intel FPGA IP Core 4.1.9.2. PTP Transmit Functionality 4.1.9.3. PTP Receive Functionality 4.1.9.4. External Time-of-Day Module for 1588 PTP Variations 4.1.9.5. PTP Timestamp and TOD Formats 4.1.9.6. Design Considerations in PTP
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers 6.4. Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. PHY Interface Signals 6.7. 1588 PTP Interface Signals 6.8. Miscellaneous Status and Debug Signals 6.9. Reset Signals
6.4. Transceiver Reconfiguration Signals x
6.4.1. Accessing the Native PHY Registers in H-Tile Devices 6.4.2. Accessing the Native PHY Registers in L-Tile Devices
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control Registers 7.5. Statistics Registers 7.6. 1588 PTP Registers 7.7. TX Reed-Solomon FEC Registers 7.8. RX Reed-Solomon FEC Registers
7.5. Statistics Registers x
7.5.1. TX Statistics Registers 7.5.2. RX Statistics Registers
8. Debugging the Link x
8.1. Error Insertion Test and Debugging
1. About the 25G Ethernet Intel FPGA IP
2. Getting Started
3. 25G Ethernet Intel FPGA IP Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide Archives
10. Document Revision History for the 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide

7.3. RX MAC Registers

Table 27.  RX MAC Registers
Addr Name Description Reset Access
0x500 RXMAC_REVID

RX MAC revision ID for 25G Ethernet IP core.

0x0504 2018

RO
0x501 RXMAC_SCRATCH Scratch register available for testing. 0x0000 0000 RW
0x502 RXMAC_NAME_0

First 4 characters of IP core variation identifier string, "25gMACRxCSR".

0x3235 674D

RO
0x503 RXMAC_NAME_1 Next 4 characters of IP core variation identifier string, "ACRx". 0x4143 5278

RO
0x504 RXMAC_NAME_2 Final 4 characters of IP core variation identifier string, "0CSR". The "0" is unprintable. 0x0043 5352

RO
0x506 MAX_RX_SIZE_CONFIG Specifies the maximum frame length available. The MAC asserts l1_rx_error[3] when the length of the received frame exceeds the value of this register.

If the IP core receives an Ethernet frame of size greater than the number of bytes specified in this register, and the IP core includes statistics registers, the IP core increments the 64-bit CNTR_RX_OVERSIZE counter.

0xXXXX 2580 6

RW
0x507 MAC_CRC_CONFIG The RX CRC forwarding configuration register. The following encodings are defined:
  • 1'b0: Remove RX CRC, do not forward it to the RX client interface
  • 1'b1: Retain RX CRC, forward it to the RX client interface
In either case, the IP core checks the incoming RX CRC and flags errors. 		31'hX1'b0 6

RW
0x508 LINK_FAULT

Link Fault Status Register.

For regular (non-unidirectional) Link Fault, implements IEEE 802.3 Ethernet Clause 46.

For unidirectional Link Fault, implements IEEE 802.3 Ethernet Clause 66.

If you turn on Enable link fault generation, the following bit fields are defined:
  • Bit[0]: A bit value of 1 indicates local fault is detected.
  • Bit[1]: A bit value of 1 indicates remote fault is detected.

If you disable Enable link fault generation, bit[0] and [1] are always to zero.

30'hX2'b00 6

RO
0x50A RXMAC_CONTROL RX MAC Control Register. A single bit is defined:
  • Bit [1]: VLAN detection disabled. This bit is deasserted by default implying VLAN detection is enabled.
  • Bit [4]: Enable check for Preamble. By default, Preamble check is turned off. Write 1'b1 to this bit to enable preamble checking. This bit is a don't care when you turn on Enable Preamble Passthrough.
27'hX_5'b0XX0X 6 RW
6 X means "Don't Care".
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