25G Ethernet Intel® Stratix® 10 FPGA IP User Guide

ID 683154
Date 9/15/2021
Public
Document Table of Contents

7.3. RX MAC Registers

Table 27.  RX MAC Registers
Addr Name Description Reset Access
0x500 RXMAC_REVID

RX MAC revision ID for 25G Ethernet IP core.

0x0504 2018

RO
0x501 RXMAC_SCRATCH Scratch register available for testing. 0x0000 0000 RW
0x502 RXMAC_NAME_0

First 4 characters of IP core variation identifier string, "25gMACRxCSR".

0x3235 674D

RO

0x503 RXMAC_NAME_1 Next 4 characters of IP core variation identifier string, "ACRx". 0x4143 5278

RO

0x504 RXMAC_NAME_2 Final 4 characters of IP core variation identifier string, "0CSR". The "0" is unprintable. 0x0043 5352

RO

0x506 MAX_RX_SIZE_CONFIG Specifies the maximum frame length available. The MAC asserts l1_rx_error[3] when the length of the received frame exceeds the value of this register.

If the IP core receives an Ethernet frame of size greater than the number of bytes specified in this register, and the IP core includes statistics registers, the IP core increments the 64-bit CNTR_RX_OVERSIZE counter.

0xXXXX 2580 6

RW

0x507 MAC_CRC_CONFIG The RX CRC forwarding configuration register. The following encodings are defined:
  • 1'b0: Remove RX CRC, do not forward it to the RX client interface
  • 1'b1: Retain RX CRC, forward it to the RX client interface
In either case, the IP core checks the incoming RX CRC and flags errors.
31'hX1'b0 6

RW

0x508 LINK_FAULT

Link Fault Status Register.

For regular (non-unidirectional) Link Fault, implements IEEE 802.3 Ethernet Clause 46.

For unidirectional Link Fault, implements IEEE 802.3 Ethernet Clause 66.

If you turn on Enable link fault generation, the following bit fields are defined:
  • Bit[0]: A bit value of 1 indicates local fault is detected.
  • Bit[1]: A bit value of 1 indicates remote fault is detected.

If you disable Enable link fault generation, bit[0] and [1] are always to zero.

30'hX2'b00 6

RO

0x50A RXMAC_CONTROL RX MAC Control Register. A single bit is defined:
  • Bit [1]: VLAN detection disabled. This bit is deasserted by default implying VLAN detection is enabled.
  • Bit [4]: Enable check for Preamble. By default, Preamble check is turned off. Write 1'b1 to this bit to enable preamble checking. This bit is a don't care when you turn on Enable Preamble Passthrough.
27'hX_5'b0XX0X 6 RW
6 X means "Don't Care".

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