25G Ethernet Intel® Stratix® 10 FPGA IP User Guide

ID 683154
Date 9/15/2021
Public
Document Table of Contents

1.4.1. Simulation Environment

Intel® performs the following tests on the 25G Ethernet Intel FPGA IP core in the simulation environment using internal and third-party standard bus functional models (BFM):

  • Constrained random tests that cover randomized frame size and contents.
  • Assertion based tests to confirm proper behavior of the IP core with respect to the specification.
  • Extensive coverage of our runtime configuration space and proper behavior in all possible modes of operation.

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