25G Ethernet Intel® Stratix® 10 FPGA IP User Guide

ID 683154
Date 9/15/2021
Public
Document Table of Contents

7.7. TX Reed-Solomon FEC Registers

Table 34.  TX Reed-Solomon FEC Registers
Addr Name Description Reset Access
0xC00 REVID Reed-Solomon FEC TX module revision ID.

0x0504_2018

RO
0xC01 TX_RSFEC_NAME_0 First 4 characters of IP core variation identifier string, "25geRSFECoTX". 0x3235_6765 RO
0xC02 TX_RSFEC_NAME_1 Middle 4 characters of IP core variation identifier string, "25geRSFECoTX". 0x5253_4645 RO
0xC03 TX_RSFEC_NAME_2 Final 4 characters of IP core variation identifier string, "25geRSFECoTX". 0x436F_5458 RO
0xC04 ERR_INS_EN
Configuration register to enable error insertion in RS-FEC transmitter. Writing 1'b1 enables the feature. Writing 1'b0 disables it. The following encodings are defined:
  • Bit[4]: Enable error insertion for single FEC codeword. Bit self-clears after error is inserted.
  • Bit[0]: Enable error insertion for every FEC codeword.
  • All other bits: Reserved.
0x00000000 RW
0xC05 ERR_MASK

Specifies the bit masks for symbols and bits in a group for error injection. Each FEC codeword consists of 528 symbols of 10 bits each. The encoder works on groups of 8 symbols (80 bits). Therefore, each FEC codeword consists of 66 groups. Writing 1'b1 enables the feature. Writing 1'b0 disables it. The following encodings are defined:

  • Bits[25:16]: Bit mask.
  • Bits[15:8]: Symbol mask.
  • Bits[6:0]: Group number (0-65).
  • Other bits: Reserved.
0x00000000 RW
0xC06 BYPASS_RSFEC

Bypass RS-FEC core. Used by both TX and RX RS-FEC cores. Writing 1'b1 enables the feature. Writing 1'b0 disables it. The following encodings are defined:

  • Bit[0]: Bypass RS-FEC core.
  • All other bits: Reserved.
0x00000000 RW

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