25G Ethernet Intel® Stratix® 10 FPGA IP User Guide

ID 683154
Date 9/15/2021
Public
Document Table of Contents

7.6. 1588 PTP Registers

The 1588 PTP registers together with the 1588 PTP signals process and provide Precision Time Protocol (PTP) timestamp information as defined in the IEEE 1588-2008 Precision Clock Synchronization Protocol for Networked Measurement and Control Systems Standard. The 1588 PTP module provides you the support to implement the 1588 Precision Time Protocol in your design.

Table 32.  TX 1588 PTP Registers

Addr

Name

Bit

Description

HW Reset Value

Access

0xA00 TXPTP_REVID [31:0] IP core revision ID.

0x0504_2018

RO
0xA01 TXPTP_SCRATCH [31:0] Scratch register available for testing. 32'b0 RW
0xA02 TXPTP_NAME_0 [31:0] First 4 characters of IP core variation identifier string "25GETXPTPCSR"

0x3235_4745

RO
0xA03 TXPTP_NAME_1 [31:0] Next 4 characters of IP core variation identifier string "25GETXPTPCSR"

0x5458_5054

RO
0xA04 TXPTP_NAME_2 [31:0] Final 4 characters of IP core variation identifier string "25GETXPTPCSR"

0x5043_5352

RO
0xA05 TX_PTP_CLK_PERIOD [19:0] clk_txmac clock period.

Bits[19:16]: nanoseconds (ns)

Bits[15:0]: fraction of nanosecond

The value of TX_PTP_CLK_PERIOD is speed dependent and needs to be reconfigured during speed switching.

  • 25G speed: 2.56 ns
  • 10G speed: 6.4 ns
0x28F5C RW

0xA06–0xA0A

Reserved   Reserved 96'b0 RO
0xA0B TX_PTP_ASYM_DELAY [18:0] Asymmetry adjustment as required for delay measurement. The IP core adds this value to the final delay.
  • Bit[18]: The value of 1 enables the feature and the value of 0 disables the feature.
  • Bit[17]: The value of 1 indicates subtraction and the value of 0 indicates addition. Depending on the value of this bit, the value in bits [16:0] is added to or subtracted from the final delay.
  • Bits[16:0]: Asymmetry adjustment in nanoseconds.
19'b0 RW
0xA0C TX_PTP_PMA_LATENCY [31:0] Latency through the TX PMA. This is the delay from the TX PCS output to the tx_serial pin.
  • Bits[31:16]: Full nanoseconds (ns)
  • Bits[15:0]: Fraction of a nanosecond

In Intel® Stratix® 10 devices, the TX_PTP_PMA_LATENCY value is speed dependent and needs to be reconfigured during speed switching. The following are the TX PMA latency values for 25G and 10G speed rates:

25G speed:
  • Digital delay: 187 UI
    Note: 1 UI is approximately 38.8 ps.
  • Analog delay:
    • ES silicon: 3.2 ns
    • Production silicon: 4.44 ns
  • Total delay:
    • ES silicon: 10.456 ns
    • Production silicon: 11.7 ns
10G speed:
  • Digital delay: 187 UI
    Note: 1 UI is approximately 97 ps.
  • Analog delay:
    • ES silicon: 2.196 ns
    • Production silicon: 5.3 ns
  • Total delay:
    • ES silicon: 20.335 ns
    • Production silicon: 23.439 ns

32'b0 RW
Table 33.  RX 1588 PTP Registers

Addr

Name

Bit

Description

HW Reset Value

Access

0xB00 RXPTP_REVID [31:0] IP core revision ID.

0x0504 2018

RO
0xB01 RXPTP_SCRATCH [31:0] Scratch register available for testing. 32'b0 RW
0xB02 RXPTP_NAME_0 [31:0] First 4 characters of IP core variation identifier string "25GERXPTPCSR"

0x3235_4745

RO
0xB03 RXPTP_NAME_1 [31:0] Next 4 characters of IP core variation identifier string "25GERXPTPCSR"

0x5258_5054

RO
0xB04 RXPTP_NAME_2 [31:0] Final 4 characters of IP core variation identifier string "25GERXPTPCSR"

0x5043_5352

RO
0xB05 RX_PTP_CLK_PERIOD [19:0] clk_rxmac clock period.

Bits [19:16]: Full nanoseconds (ns)

Bits [15:0]: Fraction of a nanosecond

The value of RX_PTP_CLK_PERIOD is speed dependent and needs to be reconfigured during speed switching.

  • 25G speed: 2.56 ns
  • 10G speed: 6.4 ns
0x28F5C RW
0xB06 RX_PTP_PMA_LATENCY [31:0] Latency through the RX PMA. This is the delay from the rx_serial pin to the RX PCS input.
  • Bits[31:16]: Full nanoseconds
  • Bits[15:0]: Fraction of a nanosecond

In Intel® Stratix® 10 devices, the RX_PTP_PMA_LATENCY value is speed dependent and needs to be reconfigured during speed switching. The following are the RX PMA latency values for 25G and 10G speed rates:

25G speed:
  • Digital delay: 104.5 UI
    Note: 1 UI is approximately 38.8 ps.
  • Analog delay:
    • ES silicon: 0.139 ns
    • Production silicon: 1.38 ns
  • Total delay:
    • ES silicon: 4.194 ns
    • Production silicon: 5.435 ns
10G speed:
  • Digital delay: 104.5 UI
    Note: 1 UI is approximately 97 ps.
  • Analog delay:
    • ES silicon: -1.194 ns
    • Production silicon: 1.91 ns
  • Total delay:
    • ES silicon: 8.943 ns
    • Production silicon: 12.047 ns

32'b0 RW

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