25G Ethernet Intel® Stratix® 10 FPGA IP User Guide

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ID 683154
Date 9/15/2021
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Document Table of Contents
Document Table of Contents x
1. About the 25G Ethernet Intel FPGA IP 2. Getting Started 3. 25G Ethernet Intel FPGA IP Parameters 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Debugging the Link 9. 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide Archives 10. Document Revision History for the 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide
1. About the 25G Ethernet Intel FPGA IP x
1.1. Release Information 1.2. Features 1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support 1.4. IP Core Verification 1.5. Performance and Resource Utilization
1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support x
1.3.1. 25G Ethernet Intel FPGA IP Core Device Family Support 1.3.2. 25G Ethernet Intel FPGA IP Core Device Speed Grade Support
1.4. IP Core Verification x
1.4.1. Simulation Environment 1.4.2. Compilation Checking 1.4.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the Intel® Stratix® 10 IP Core Parameters and Options 2.3. Simulating the IP Core 2.4. Generated File Structure 2.5. Integrating Your IP Core in Your Design 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Adding the External Time-of-Day Module for Variations with 1588 PTP Feature 2.5.4. Placement Settings for the 25G Ethernet Intel FPGA IP Core
4. Functional Description x
4.1. 25G Ethernet Intel FPGA IP Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. 25G Ethernet Intel FPGA IP Core Functional Description x
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath 4.1.2. 25 GbE TX PCS 4.1.3. TX RS-FEC 4.1.4. 25G Ethernet Intel FPGA IP Core RX MAC Datapath 4.1.5. Link Fault Signaling Interface 4.1.6. 25 GbE RX PCS 4.1.7. RX RS-FEC 4.1.8. Flow Control 4.1.9. 1588 Precision Time Protocol Interfaces
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion 4.1.1.4. Frame Check Sequence (CRC32) Insertion
4.1.4. 25G Ethernet Intel FPGA IP Core RX MAC Datapath x
4.1.4.1. IP Core Preamble Processing 4.1.4.2. IP Core Malformed Packet Handling 4.1.4.3. Length/Type Field Processing 4.1.4.4. RX CRC Checking and Dynamic Forwarding
4.1.4.3. Length/Type Field Processing x
4.1.4.3.1. Length Checking
4.1.8. Flow Control x
4.1.8.1. TX Pause/PFC Flow Control Frame Transmission Request 4.1.8.2. XON/XOFF Pause Frames
4.1.9. 1588 Precision Time Protocol Interfaces x
4.1.9.1. Implementing a 1588 System That Includes a 25G Ethernet Intel FPGA IP Core 4.1.9.2. PTP Transmit Functionality 4.1.9.3. PTP Receive Functionality 4.1.9.4. External Time-of-Day Module for 1588 PTP Variations 4.1.9.5. PTP Timestamp and TOD Formats 4.1.9.6. Design Considerations in PTP
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers 6.4. Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. PHY Interface Signals 6.7. 1588 PTP Interface Signals 6.8. Miscellaneous Status and Debug Signals 6.9. Reset Signals
6.4. Transceiver Reconfiguration Signals x
6.4.1. Accessing the Native PHY Registers in H-Tile Devices 6.4.2. Accessing the Native PHY Registers in L-Tile Devices
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control Registers 7.5. Statistics Registers 7.6. 1588 PTP Registers 7.7. TX Reed-Solomon FEC Registers 7.8. RX Reed-Solomon FEC Registers
7.5. Statistics Registers x
7.5.1. TX Statistics Registers 7.5.2. RX Statistics Registers
8. Debugging the Link x
8.1. Error Insertion Test and Debugging
1. About the 25G Ethernet Intel FPGA IP
2. Getting Started
3. 25G Ethernet Intel FPGA IP Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide Archives
10. Document Revision History for the 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide

7.4. Pause/PFC Flow Control Registers

Some of the registers in this table cannot be updated during normal operation. To ensure correct operation, perform a soft reset by writing Bit[0] of the PHY_CONFIG (0x310) after updating registers that cannot be changed dynamically.
Table 28.  TX Flow Control Registers
Addr Bit Name Description Reset Access
0x600 31:0 TX Flow Control Revision ID

Specifies the revision ID, "25GEFCTx CSR".

0x0916_2016

 RO
0x601 31:0 TX Flow Control Scratch Pad Scratch register for testing. 0 RW
0x602 31:0 TX Flow Control IP Core Variant 0

Specifies first 4 characters of IP core variation identifier ASCII string, "25GE ".

0x3235_4745

 RO
0x603 31:0 TX Flow Control IP Core Variant 1 Next 4 characters of IP core variation identifier ASCII string, "FCTx". 0x4643_5478 RO
0x604 31:0 TX Flow Control IP Core Variant 2

Final 4 characters of IP core variation identifier ASCII string, "0CSR". The "0" is unprintable.

0x0043_5352 RO
0x605

(FCQN-1):0

TX Flow Control Enable

Enables the IP core to generate XON and XOFF Pause/PFC flow control frames to the remote partner. The following encodings are defined:
  • 1'b0: XON or XOFF Pause/PFC flow control is disabled.
  • 1'b1: XON or XOFF Pause/PFC flow control is enabled.

You can change this field dynamically.

1'b1 in each bit that corresponds to a queue

RW

31:FCQN

 Reserved Reserved 0 RO
0x606

(FCQN-1):0

TX Flow Control CSR XON/XOFF Request 1

One bit per queue

 XON/XOF flow control frame request bit 0. Interpretation depends on whether the IP core is in 1-bit FC request mode or in 2-bit FC request mode. This register affects a flow control queue only if the corresponding bit of the TX Flow Control Enable register has the value of 1.

In 2-bit mode, in addition, this register is active for a specific flow control queue only if the corresponding bit in the TX 2-bit Flow Control Request Mode register field (bits [(FCQN-1):0] of the register at offset 0x641) specifies that the flow control logic accepts input from this register.

The following encodings are defined for 1-bit mode. The IP core reads the 1-bit mode value in TX Flow Control CSR XON/XOFF Request 0.

  • 0 = No request
  • 0 to 1 = Generate XOFF request
  • 1 = Continue to generate XOFF request
  • 1 to 0 = Generate XON request

The following encodings are defined for 2-bit mode. The IP core reads the 2-bit mode value in {TX Flow Control CSR XON/XOFF Request 1, TX Flow Control CSR XON/XOFF Request 1}.

  • 00 = No request
  • 01 = XON request
  • 10 = XOFF request
  • 11 = Invalid

You can modify the value of this field dynamically.

0 RW

15:FCQN

 Reserved Reserved 0 RO

(FCQN+15):16

TX Flow Control CSR XON/XOFF Request 1

1-bit per queue

In conjunction with Flow Control XON/XOFF Request 0 specifies a 2-bit request for XON/XOFF flow control frame transmission. This bit is the upper bit of the 2-bit control field.

You can change the value of this field dynamically.

0 RW

31:(FCQN+16)

 Reserved Reserved 0 RO
0x607 31:0 Reserved Reserved N/A RO
0x608 31:0 Reserved Reserved N/A RO
0x609 31:0 Reserved Reserved N/A RO
0x60A 0

TX Pause Enable

1-bit

Determines whether receiving a valid Pause frame stops TX user data transmission.

1'b0: Transmission is not stopped

1'b1: Transmission stops

You cannot change the value of this field dynamically.

0 RW
31:1 Reserved Reserved 0 RO
0x60B 31:0 Reserved Reserved N/A RO
0x60C 31:0 Reserved Reserved N/A RO
0x60D 31:0 TX Flow Control Destination Address Lower

Specifies the 48-bit Destination Address of the flow control frame. Contains the 32 LSB of the address field.

You cannot modify the value of this field dynamically.

0xC2000001 RW
0x60E 15:0 TX Flow Control Destination Address Upper

Specifies the 48-bit Destination Address of flow control frame. Contains the 16 MSB of the address field.

You cannot modify the value of this field dynamically.

0x0180 RW
31:16 Reserved Reserved 0 RO
0x60F 31:0 TX Flow Control Source Address Lower

Specifies the 48-bit Source Address of flow control frame. Contains the 32 LSB of the address field.

0xCBFC5ADD RW
0x610 15:0 TX Flow Control Source Address Upper

Specifies the 48-bit Source Address of flow control frame. Contains the 16 MSB of the address field.

You cannot modify the value of this field dynamically.

0xE100 RW
31:16 Reserved Reserved 0 RO

0x620, 0x621, …, 0x620+(FCQN-1 )

15:0

TX Flow Control Quanta

16-bit per queue

Specifies the pause quanta of Pause/PFC flow control frames to be sent to remote partner.

You cannot modify the value of this field dynamically.

0xFFFF RW
31:16 Reserved Reserved 0 RO
0x628, 0x629, …, 0x628+(FCQN-1 ) 15:0

TX Flow Control Signal XOFF Request Hold Quanta

16-bit per queue

Specifies the separation between 2 consecutive XOFF flow control frames.

You cannot modify the value of this field dynamically.

0xFFFF RW
31:16 Reserved Reserved 0 RO
0x640 0

TX Flow Control Select

1-bit

Specifies whether the TX hardware generates Pause or PFC frames. Affects only PFC Queue 0.

Usage example:

You can synthesize a single PFC queue and use it for both Pause and PFC purpose.

1'b0: Pause

1'b1: PFC

You cannot modify the value of this field dynamically.

1 RW
31:1 Reserved. Reserved. 0 RO
0x641 (FCQN-1):0

TX 2-bit Flow Control Request Mode

1-bit per queue

Determines whether the TX Flow Control CSR XON/XOFF Request register or the pause_insert_tx0 and pause_insert_tx1 signals control XON/XOFF mode in 2-bit control mode.

1'b0: The pause_insert_tx0 and pause_insert_tx1 signals control requests

1'b1: The TX Flow Control CSR XON/XOFF Request register fields control requests

You cannot modify the value of this field dynamically.

0 RW
16

TX Flow Control Request Mode

1 bit for all queues

Determines whether the IP core is in TX flow control 1-bit mode or 2-bit mode.

1'b0: Use 1-bit mode to make TX flow control requests

1'b1: Use 2-bit mode to make TX flow control requests

0 RW
31:17 Reserved Reserved 0 RO
Table 29.  RX Flow Control Registers
Addr Bit Name Description Reset Access
0x700 31:0 RX Flow Control Revision ID

Provides the flow control revision, "25GEFCRx CSR".

0x0916_2016 RO
0x701 31:0 RX Flow Control Scratch Pad Provides a register for debug. 0 RW
0x702 31:0 RX Flow Control IP Core Variant 0

First 4 characters of IP core variation identifier ASCII string,

"25GE".

0x3235_4745

 RO
0x703 31:0 RX Flow Control IP Core Variant 1 Next 4 characters of IP core variation identifier ASCII string, "FCRx". 0x4643_5278 RO
0x704 31:0 RX Flow Control IP Core Variant 2 Final 4 characters of IP core variation identifier ASCII string, "0CSR". The "0" is unprintable. 0x0043_5352 RO
0x705 (FCQN-1):0]

RX PFC Enable

1 bit per queue

Determines whether receiving a valid PFC frame causes the PFC duration user interface to indicate a valid pause quanta duration to the user logic.

1'b0: Disable

1'b1: Enable

You cannot modify the value of this field dynamically.

1'b1 in each bit that corresponds to a queue RW
31:FCQN 8 Reserved Reserved 0 RO
0x706 31:0 Reserved Reserved N/A RO
0x707 31:0 RX Flow Control Destination Address Lower

Specifies the 48-bit Destination Address of the flow control frame. Contains the 32 LSB of the address field.

You cannot modify the value of this field dynamically.

0xC2000001 RW
0x708 15:0 RX Flow Control Destination Address Upper

Specifies the 48-bit Destination Address of flow control frame. Contains the 16 MSB of the address field.

You cannot modify the value of this field dynamically.

0x0180 RW
31:16 Reserved Reserved 0 RO
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