25G Ethernet Intel® Stratix® 10 FPGA IP User Guide

ID 683154
Date 9/15/2021
Public
Document Table of Contents

4.1.9.6. Design Considerations in PTP

  • When the PTP option is enabled together with RS-FEC option, there is no accuracy loss by neglecting bit shift due to transcode effect with the assumption transcode effect will be totally reversed at the receiver side.
  • When the PTP option is enabled together with 10/25G switching option, tx_period, rx_period, tx_pma_delay, and rx_pma_delay need to be reconfigured according to the running speed. Refer to the 1588 PTP Registers section for the correct value.

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