1. About the 25G Ethernet Intel FPGA IP
|Intel® Quartus® Prime Design Suite 21.1|
|IP Version 19.4.0|
The 25G Ethernet Intel FPGA IP implements the 25G & 50G Ethernet Specification, Draft 1.6 from the 25 Gigabit Ethernet Consortium and the IEEE 802.3by 25Gb Ethernet specification. The IP includes an option to support unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard. The MAC client side interface for the 25G Ethernet Intel FPGA IP is a 64-bit Avalon® streaming interface. It maps to one 25.78125 Gbps transceiver. The IP optionally includes the IEEE 802.3-2018 Clause 108 Reed-Solomon forward error correction (RS-FEC) for support of IEEE802.3-2018 Clause 107 25GBASE-R PCS. IEEE 802.3 Clause 73 Auto-Negotiation and IEEE 802.3 Clause 74 CR/KR-FEC are not supported. Transceiver interface to 25GBASE-SR optical Physical Medium Dependent (PMD) transceiver is supported.
The IP provides standard media access control (MAC) and physical coding sublayer (PCS), Reed-Solomon Forward Error Correction (RS-FEC), and PMA functions shown in the following block diagrams. The PHY comprises the PCS, optional RS-FEC, and elective PMA.
- To configure the IP between 10G and 25G, follow the reconfiguration sequence as defined in the L- and H-Tile Transceiver PHY User Guide. For simplification, refer to the reconfiguration sequencer module from the design example, which is not part the IP.
- For MAC + PCS core variant, follow the reset sequence guideline as defined in Recommended Reset Sequence of the L- and H-Tile Transceiver PHY User Guide to ensure the 25G Ethernet Intel FPGA IP is having a proper reset sequence.
The following block diagram shows an example of a network application with 25G Ethernet Intel FPGA IP MAC and PHY.
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