25G Ethernet Intel® Stratix® 10 FPGA IP User Guide

ID 683154
Date 9/15/2021
Public
Document Table of Contents

7.5. Statistics Registers

The 25G Ethernet Intel FPGA IP statistics registers count Ethernet traffic and errors. The 64-bit statistics registers are designed to roll over, to ensure timing closure on the FPGA. However, these registers should never roll over if the link is functioning properly. The statistics registers check the size of frames, which includes the following fields:

  • Size of the destination address
  • Size of the source address
  • Size of the data
  • Four bytes of CRC

The statistics counters module is a synthesis option. The statistics registers are counters that are implemented inside the CSR. When you turn on the Enable MAC statistics counters parameter in the 25G Ethernet Intel FPGA IP parameter editor, the counters are implemented in the CSR. When you turn off the Enable MAC statistics counters parameter in the 25G Ethernet Intel FPGA IP parameter editor, the counters are not implemented in the CSR, and read access to the counters returns undefined results.

After system power-up, the statistics counters have random values. You must clear these registers and confirm the system is stable before using their values. To clear the registers, use any of the following methods:

  1. Assert csr_rst_n to clear both the TX and RX statistic counters.
  2. Assert tx_rst_n to clear the TX statistic counters.
  3. Assert rx_rst_n to clear the RX statistic counters.
  4. Write 1'b1 to bit[0], eio_sys_rst of the PHY_CONFIG (0x310) register to clear both the TX and RX statistic counters.
  5. Write 1'b1 to bit[1], soft_txp_rst of the PHY_CONFIG (0x310) register to clear the TX statistic counters.
  6. Write 1'b1 to bit[2], soft_rxp_rst of the PHY_CONFIG (0x310) register to clear the RX statistic counters.
  7. Write 1'b1 to bit[0] of the CNTR_TX_CONFIG (0x845) to clear the TX statistic counters.
  8. Write 1'b1 to bit[0] of the CNTR_RX_CONFIG (0x945) to clear the RX statistic counters.

The configuration register at offset 0x845 allows you to clear all of the TX statistics counters. The configuration register at offset 0x945 allows you to clear all of the RX statistics counters. If you exclude these registers, you can monitor the statistics counter increment vectors that the IP core provides at the client side interface and maintain your own counters.

Reading the value of a statistics register does not affect its value.

To ensure that the counters you read are consistent, you should issue a shadow request to create a snapshot of all of the TX or RX statistics registers, by setting bit [2] of the configuration register at offset 0x845 or 0x945, respectively. Until you reset this bit, the counters continue to increment but the readable values remain constant. You can read bit [1] of the status register at offset 0x846 or 0x946, respectively, to confirm your shadow request has been granted or released.

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