25G Ethernet Intel® Stratix® 10 FPGA IP User Guide

ID 683154
Date 9/15/2021
Public
Document Table of Contents

2.5.4. Placement Settings for the 25G Ethernet Intel FPGA IP Core

The Quartus Prime software provides the options to specify design partitions and Logic Lock (Standard) or Logic Lock regions for incremental compilation, to control placement on the device. To achieve timing closure for your design, you might need to provide floorplan guidelines using one or both of these features.

The appropriate floorplan is always design-specific, and depends on your design.

Did you find the information on this page useful?

Characters remaining:

Feedback Message