25G Ethernet Intel® Stratix® 10 FPGA IP User Guide

ID 683154
Date 9/15/2021
Public
Document Table of Contents

4.1.7. RX RS-FEC

If you turn on Enable RS-FEC in the 25G Ethernet Intel FPGA IP parameter editor, the IP core includes Reed-Solomon forward error correction (FEC) in both the receive and transmit datapaths.
The IP core implements Reed-Solomon FEC per Clause 108 of the IEEE Standard 802.3by. The Reed-Solomon FEC algorithm includes the following modules:
  • Alignment marker lock
  • 66:80 gearbox
  • High-speed Reed-Solomon decoder
  • 80:257 gearbox
  • 256B/257B to 64B/66B Transcoding

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