25G Ethernet Intel® Stratix® 10 FPGA IP User Guide

ID 683154
Date 9/15/2021
Public
Document Table of Contents

6.6. PHY Interface Signals

Table 20.  Signals of the PHY InterfaceThis table lists the PHY interface signals. These interface signals are only applicable to the 25G Ethernet Intel FPGA IP with MAC and PCS core variant. For more information on these interface signals, refer to the Intel® Stratix® 10 L- and H-Tile Transceiver PHY User Guide.
Signal Direction Description
tx_clkout Input

When you turn on Enable IEEE 1588, this clock is a TX transceiver parallel clock. The frequency of this clock is 402.832 MHz for 25G data rate and 161.132 MHz for 10G rate.

When Enable IEEE 1588 is turned off, this clock is used by the MAC transmitter (TX MAC). The frequency of this clock is 390.625 MHz for 25G data rate and 156.25 MHz for 10G data rate.

tx_clkout2 Input Clock for the TX MAC when you turn on Enable IEEE 1588. The frequency of this clock is 390.625 MHz for 25G data rate and 156.25 MHz for 10G data rate.

This port is unused when Enable IEEE 1588 is turned off.

rx_clkout Input

When you turn on Enable IEEE 1588, this clock is a RX transceiver parallel clock. The frequency of this clock is 402.832 MHz for 25G data rate and 161.132 MHz for 10G rate.

When Enable IEEE 1588 is turned off, this clock is used by the MAC receiver (RX MAC). The frequency of this clock is 390.625 MHz for 25G data rate and 156.25 MHz for 10G data rate.

rx_clkout2 Input Clock for the RX MAC when you turn on Enable IEEE 1588. The frequency of this clock is 390.625 MHz for 25G data rate and 156.25 MHz for 10G data rate.

This port is unused when Enable IEEE 1588 is turned off.

rvalid Input Indication for RX valid data.
tvalid_phy Output Indicates valid data output towards PHY.
tx_parallel_data_phy[63:0] Output TX parallel data output from the FPGA fabric to PHY.
tx_control_phy[1:0] Output TX control character output from the FPGA fabric to PHY.

When you turn on Enable RS-FEC, the tx_control_phy does not transmit the control character to link partner. The 66-bits output from the RS-FEC is split into tx_parallel_data_phy[63:0] and tx_control_phy[1:0], where the tx_control_phy[1:0] is the most upper 2-bits of the 66-bits data bus, for example, {tx_control_phy[1:0], tx_parallel_data_phy[63:0]}.

For details about the TX RS-FEC, refer to the TX RS-FEC section.

rx_parallel_data_phy[63:0] Input RX parallel data input from the PHY to FPGA fabric.
rx_control_phy[1:0] Input RX control character input from the PHY to FPGA fabric.

When you turn on Enable RS-FEC, the rx_control_phy does not receive the control character from link partner. The 66-bits input to the RS-FEC is split into rx_parallel_data_phy[63:0] and rx_control_phy[1:0], where the rx_control_phy[1:0] is the most upper 2-bits of the 66-bits data bus, for example, {rx_control_phy[1:0], rx_parallel_data_phy[63:0]}.

For details about the RX RS-FEC, refer to the RX RS-FEC section.

tx_fifo_latency_pulse Input Latency pulse for TX Core FIFO.
tx_pcs_fifo_latency_pulse Input Latency pulse for TX PCS FIFO.
rx_fifo_latency_pulse Input Latency pulse for RX Core FIFO.
rx_pcs_fifo_latency_pulse Input Latency pulse for RX PCS FIFO.
rx_bitslip Output Indicates bit slip enable status.
rx_digitalreset Input Resets the PCS RX portion of the transceiver PHY.
tx_digitalrest Input Resets the PCS TX portion of the transceiver PHY.
rx_is_lockedtodata Input Indicates the status of RX CDR lock on data.
rx_set_locktoref Output Indicates the status of RX CDR lock to reference clock.
rx_seriallpbken Output Status for Internal Serial Loopback.
tx_ready Input Indication for external PMA TX Ready.
rx_ready Input Indication for external PMA RX Ready
phy_reset Output Reset signal for PHY.
tx_empty_phy Input Indication for TX Core FIFO empty.
tx_pempty_phy Input Indication for TX Core FIFO partially empty.
tx_full_phy Input Indication for TX Core FIFO full.
tx_pfull_phy Input Indication for TX Core FIFO partially full.
rx_empty_phy Input Indication for RX Core FIFO empty.
rx_pempty_phy Input Indication for RX Core FIFO partially empty.
rx_full_phy Input Indication for RX Core FIFO full.
rx_pfull_phy Input Indication for RX Core FIFO partially full.

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