25G Ethernet Intel® Stratix® 10 FPGA IP User Guide

ID 683154
Date 9/15/2021
Public
Document Table of Contents

2.5.2. Adding the Transceiver PLL

The transceiver channels in the Intel® Stratix® 10 devices require an external PLL to drive the TX transceiver serial clock, in order to compile and to function correctly in hardware. In many cases, the same PLL can be shared with an additional transceiver in your design.

Figure 9. PLL Configuration Example for 25G ConfigurationThe TX transceiver PLL is instantiated with an ATX PLL IP core. The TX transceiver PLL must always be instantiated outside the 25G Ethernet Intel FPGA IP core.
Figure 10. PLL Configuration Example for 10G/25G ConfigurationThe TX transceiver PLL is instantiated with an ATX PLL IP core. The TX transceiver PLL must always be instantiated outside the 25G Ethernet Intel FPGA IP core.

You can use the IP Catalog to create a transceiver PLL.

  • Select L-Tile/H-Tile Transceiver ATX PLL Intel® Stratix® 10 FPGA IP.
  • In the parameter editor, set the following parameter values:
    • For 25G configuration:
      • PLL output frequency to 12890.625 MHz. The transceiver performs dual edge clocking, using both the rising and falling edges of the input clock from the PLL. Therefore, this PLL output frequency setting supports a 25.78125 Gbps data rate through the transceiver.
      • Primary PLL clock output buffer to GXT clock output buffer.
      • Turn on Enable GXT local clock output port (tx_serial_clk_gxt).
    • For 10G configuration:
      • PLL output frequency to 5156.25 MHz. The transceiver performs dual edge clocking, using both the rising and failing edges of the input clock from the PLL. Therefore, this PLL output frequency setting supports a 10.3125 Gbps data rate through the transceiver.
      • Primary PLL clock output buffer to GX clock output buffer.
      • Turn on Enable GX local clock output port (tx_serial_clk).
    • PLL auto mode reference clock frequency (integer) to 644.53125 or 322.265625 MHz.

You must connect the ATX PLL to the 25G Ethernet Intel FPGA IP core as follows:

  • Connect the clock output port of the ATX PLL to the tx_serial_clk input port of the 25G Ethernet Intel FPGA IP core.
  • If the Enable 10G/25G dynamic rate switching option is turned on:
    • Connect the clock output port of the ATX PLL with 25G configuration to tx_serial_clk0 input port of the 25G Ethernet Intel FPGA IP core.
    • Connect the clock output port of the ATX PLL with 10G configuration to tx_serial_clk1 input port of the 25G Ethernet Intel FPGA IP core.
  • Connect the pll_locked output port of the ATX PLL to the tx_pll_locked input port of the 25G Ethernet Intel FPGA IP core.
  • Drive the ATX PLL reference clock port and the 25G Ethernet Intel FPGA IP core clk_ref input port with the same clock. The clock frequency must be the frequency you specify for the ATX PLL IP core PLL auto mode reference clock frequency (integer) parameter.

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