25G Ethernet Intel® Stratix® 10 FPGA IP User Guide

ID 683154
Date 9/15/2021
Public
Document Table of Contents

2.5.3. Adding the External Time-of-Day Module for Variations with 1588 PTP Feature

25G Ethernet Intel FPGA IP cores that include the 1588 PTP module require an external time-of-day (TOD) module to provide a continuous flow of current time-of-day information. The TOD module must update the time-of-day output value on every clock cycle, and must provide the TOD value in the V2 format (96 bits) or the 64-bit TOD format, or both.

Intel provides the following components that you can combine to create the TOD module the 25G Ethernet Intel FPGA IP core requires:

  • A simple TOD clock module, available from the IP Catalog (Interface Protocols > Ethernet > Reference Design Components > Ethernet IEEE 1588 Time of Day Clock Intel® FPGA IP ). You can instantiate two of these clock modules and connect one to the TX MAC and the other to the RX MAC.
  • A single-format TOD synchronizer, available from the IP Catalog (Interface Protocols > Ethernet > Reference Design Components > Ethernet IEEE 1588 TOD Synchronizer Intel® FPGA IP ). This component can handle only a single TOD format. Therefore, if you set the Time of day format parameter to the value of Enable both formats, you must instantiate and connect two TOD synchronizer modules. If your IP core supports only a single TOD format, your design requires only a single TOD synchronizer module.

Each TOD synchronizer connects a master TOD clock and a slave TOD clock.

  • If you create your TOD module with a single TOD synchronizer, the master TOD clock connects to the TX MAC of the 25G Ethernet Intel FPGA IP core and the slave TOD clock connects to the RX MAC of the 25G Ethernet Intel FPGA IP core.
  • Alternatively, you can drive both the TX and RX TOD clocks from a single master TOD clock. In that case, your design must include two TOD synchronizers, one to connect the master TOD clock and the slave TX TOD clock and one to connect the master TOD clock and the slave RX TOD clock.

If your IP core supports both TOD formats, double the number of TOD synchronizers in your TOD module. The configuration you implement depends on your system design requirements for 1588 PTP functionality.

Figure 11. TOD Synchronizer and TOD Clocks in 96-Bit TOD Format DesignShows the required connections between two TOD clock components and a TOD synchronizer component in a single TOD format design. In a simple TOD module, the master TOD clock connects to the TX MAC of the IP core, and the slave TOD clock connects to the RX MAC of the IP core. If your 25G Ethernet Intel FPGA IP core supports both TOD formats, a second TOD synchronizer connects to the corresponding 64-bit time-of-day signals of the same master and slave TOD clocks.

For information about the Ethernet IEEE 1588 Time of Day Clock and Ethernet IEEE 1588 TOD Synchronizer components, and the requirements for the PLL that connects to the TOD synchronizer, refer to the Ethernet Design Example Components User Guide.

Table 12.  TOD Module Required Connections to 25G Ethernet Intel FPGA IP CoreLists the required connections between the TOD module and the 25G Ethernet Intel FPGA IP core, using signal names for TOD modules that provide both a 96-bit TOD and a 64-bit TOD. If you create your own TOD module it must have the output signals required by the 25G Ethernet Intel FPGA IP core. However, its signal names could be different than the TOD module signal names in the table. The signals that the IP core includes depend on the value you set for Time of day format in the parameter editor. For example, an RX TOD module might require only a 96-bit TOD out signal. This table does not list required connections between the TOD module and additional parts of your design.
TOD Module Signal 25GbE IP Core Signal
rst_n (input to TX and RX TOD clocks) Drive this signal from the same source as the csr_rst_n input signal to the 25G Ethernet Intel FPGA IP core.

period_rst_n (input to RX TOD clock)

reset_slave (input to Synchronizer)

Drive these signals from the same source as the rx_rst_n input signal to the 25G Ethernet Intel FPGA IP core.

period_rst_n (input to TX TOD clock)

reset_master (input to Synchronizer)

Drive these signals from the same source as the tx_rst_n input signal to the 25G Ethernet Intel FPGA IP core.
time_of_day_96b[95:0] (output from TX TOD clock) tx_time_of_day_96b_data[95:0] (input)
time_of_day_64b[63:0] (output from TX TOD clock) tx_time_of_day_64b_data[63:0] (input)
time_of_day_96b[95:0] (output from RX TOD clock) rx_time_of_day_96b_data[95:0] (input)
time_of_day_64b[63:0] (output from RX TOD clock) rx_time_of_day_64b_data[63:0] (input)

period_clk (input to TX TOD clock)

clk_master (input to Synchronizer)

clk_txmac (output)

period_clk (input to RX TOD clock)

clk_slave (input to Synchronizer)

clk_rxmac (output)

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