25G Ethernet Intel® Stratix® 10 FPGA IP User Guide

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ID 683154
Date 9/15/2021
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Document Table of Contents
Document Table of Contents x
1. About the 25G Ethernet Intel FPGA IP 2. Getting Started 3. 25G Ethernet Intel FPGA IP Parameters 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Debugging the Link 9. 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide Archives 10. Document Revision History for the 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide
1. About the 25G Ethernet Intel FPGA IP x
1.1. Release Information 1.2. Features 1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support 1.4. IP Core Verification 1.5. Performance and Resource Utilization
1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support x
1.3.1. 25G Ethernet Intel FPGA IP Core Device Family Support 1.3.2. 25G Ethernet Intel FPGA IP Core Device Speed Grade Support
1.4. IP Core Verification x
1.4.1. Simulation Environment 1.4.2. Compilation Checking 1.4.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the Intel® Stratix® 10 IP Core Parameters and Options 2.3. Simulating the IP Core 2.4. Generated File Structure 2.5. Integrating Your IP Core in Your Design 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Adding the External Time-of-Day Module for Variations with 1588 PTP Feature 2.5.4. Placement Settings for the 25G Ethernet Intel FPGA IP Core
4. Functional Description x
4.1. 25G Ethernet Intel FPGA IP Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. 25G Ethernet Intel FPGA IP Core Functional Description x
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath 4.1.2. 25 GbE TX PCS 4.1.3. TX RS-FEC 4.1.4. 25G Ethernet Intel FPGA IP Core RX MAC Datapath 4.1.5. Link Fault Signaling Interface 4.1.6. 25 GbE RX PCS 4.1.7. RX RS-FEC 4.1.8. Flow Control 4.1.9. 1588 Precision Time Protocol Interfaces
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion 4.1.1.4. Frame Check Sequence (CRC32) Insertion
4.1.4. 25G Ethernet Intel FPGA IP Core RX MAC Datapath x
4.1.4.1. IP Core Preamble Processing 4.1.4.2. IP Core Malformed Packet Handling 4.1.4.3. Length/Type Field Processing 4.1.4.4. RX CRC Checking and Dynamic Forwarding
4.1.4.3. Length/Type Field Processing x
4.1.4.3.1. Length Checking
4.1.8. Flow Control x
4.1.8.1. TX Pause/PFC Flow Control Frame Transmission Request 4.1.8.2. XON/XOFF Pause Frames
4.1.9. 1588 Precision Time Protocol Interfaces x
4.1.9.1. Implementing a 1588 System That Includes a 25G Ethernet Intel FPGA IP Core 4.1.9.2. PTP Transmit Functionality 4.1.9.3. PTP Receive Functionality 4.1.9.4. External Time-of-Day Module for 1588 PTP Variations 4.1.9.5. PTP Timestamp and TOD Formats 4.1.9.6. Design Considerations in PTP
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers 6.4. Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. PHY Interface Signals 6.7. 1588 PTP Interface Signals 6.8. Miscellaneous Status and Debug Signals 6.9. Reset Signals
6.4. Transceiver Reconfiguration Signals x
6.4.1. Accessing the Native PHY Registers in H-Tile Devices 6.4.2. Accessing the Native PHY Registers in L-Tile Devices
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control Registers 7.5. Statistics Registers 7.6. 1588 PTP Registers 7.7. TX Reed-Solomon FEC Registers 7.8. RX Reed-Solomon FEC Registers
7.5. Statistics Registers x
7.5.1. TX Statistics Registers 7.5.2. RX Statistics Registers
8. Debugging the Link x
8.1. Error Insertion Test and Debugging
1. About the 25G Ethernet Intel FPGA IP
2. Getting Started
3. 25G Ethernet Intel FPGA IP Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide Archives
10. Document Revision History for the 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide

4.1.4.3.1. Length Checking

The MAC function checks the frame and payload lengths of basic, VLAN tagged, and stacked VLAN tagged frames.

The IP core checks that the frame length is valid—is neither undersized nor oversized. A valid frame length is at least 64 (0x40) bytes and does not exceed the following maximum value for the different frame types:

  • Basic frames—The number of bytes specified in the MAX_RX_SIZE_CONFIG register.
  • VLAN tagged frames—The value specified in the MAX_RX_SIZE_CONFIG register plus four bytes.
  • Stacked VLAN tagged frames—The value specified in the MAX_RX_SIZE_CONFIG register plus eight bytes.

If the length/type field in a basic MAC frame or the client length/type field in a VLAN tagged frame has a value less than 0x600, the IP core also checks the payload length. The IP core keeps track of the payload length as it receives a frame, and checks the length against the relevant frame field. The payload length is valid if it satisfies the following conditions:

  • The actual payload length matches the value in the length/type or client length/type field.
  • Normal frames:
    • Basic frames—the payload length is between 46 (0x2E)and 1536 (0x0600) bytes, excluding 1536.
    • VLAN tagged frames—the payload length is between 42 (0x2A)and 1536 (0x0600), excluding 1536.
    • Stacked VLAN tagged frames—the payload length is between 38 (0x26) and 1536 (0x0600), excluding 1536.
  • Jumbo frames:
    • Jumbo basic frames—the payload length is between 46 (0x2E) and the value specified in the MAX_RX_SIZE_CONFIG register minus 18 bytes.
    • Jumbo VLAN tagged frames—the payload length is between 42 (0x2A) and the value specified in the MAX_RX_SIZE_CONFIG register minus 22 bytes.
    • Jumbo stacked VLAN tagged frames—the payload length is between 38 (0x26) and the value specified in the MAX_RX_SIZE_CONFIG register minus 26 bytes.

The RX MAC does not drop frames with invalid length or invalid payload length. If the frame or payload length is not valid, the MAC function asserts output error bits.

  • l1_rx_error[2]—Undersized frame.
  • l1_rx_error[3]—Oversized frame.
  • l1_rx_error[4]—Payload length error.

If the length field value is greater than the actual payload length, the IP core asserts l1_rx_error[4] . If the length field value is less than the actual payload length, the MAC RX considers the frame to have excessive padding and does not assert l1_rx_error[4] .

Note: Starting from Intel® Quartus® Prime Pro Edition software version 20.3 onwards, the MAC has a counter limit of 0xFFFF. For frames with size larger than this value, the MAC asserts oversized frame error regardless of the value programmed into MAX_RX_SIZE_CONFIG. This applies to the TX datapath as well.
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