25G Ethernet Intel® Stratix® 10 FPGA IP User Guide

ID 683154
Date 9/15/2021
Public
Document Table of Contents

7.8. RX Reed-Solomon FEC Registers

Table 35.  RX Reed-Solomon FEC Registers
Addr Name Description Reset Access
0xD00 REVID RS-FEC TX module revision ID

0x0504_2018

RO
0xD01 RX_RSFEC_NAME0 First 4 characters of IP core variation identifier string, "25geRSFECoRX". 0x3235_6765 RO
0xD02 RX_RSFEC_NAME1 Middle 4 characters of IP core variation identifier string, "25geRSFECoRX". 0x5253_4645 RO
0xD03 RX_RSFEC_NAME2 Final 4 characters of IP core variation identifier string, "25geRSFECoRX". 0x436F_5258 RO
0xD04 BYPASS_RESTART

Configuration register to bypass error correction and to restart alignment marker synchronization. Writing 1'b1 enables the feature. Writing 1'b0 disables it.The following encodings are defined:

  • Bit[0]: Bypass error correction. The RS-FEC core remains enabled but does not correct errors.
  • Bit[4]: Restarts FEC alignment marker synchronization. Bit clears after alignment marker synchronization is restarted.
  • All other bits: Reserved.
0x0000 0000 RW
0xD05 FEC_ALIGN_STATUS

Alignment marker lock status. The following encodings are defined:

  • Bit[0]: Indicates alignment marker lock status. When 1'b1, indicates alignment has been achieved.
  • All other bits: reserved
0x0000 0000 RO
0xD06 CORRECTED_CW 32-bit counter that contains the number of corrected FEC codewords processed. The value resets to zero upon read and holds at max count. 0x0000 0000 RO
0xD07 UNCORRECTED_CW 32-bit counter that contains the number of uncorrected FEC codewords processed. The value resets to zero upon read and holds at max count. 0x0000 0000 RO

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