25G Ethernet Intel® Stratix® 10 FPGA IP User Guide

Download PDF
ID 683154
Date 9/15/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the 25G Ethernet Intel FPGA IP 2. Getting Started 3. 25G Ethernet Intel FPGA IP Parameters 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Debugging the Link 9. 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide Archives 10. Document Revision History for the 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide
1. About the 25G Ethernet Intel FPGA IP x
1.1. Release Information 1.2. Features 1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support 1.4. IP Core Verification 1.5. Performance and Resource Utilization
1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support x
1.3.1. 25G Ethernet Intel FPGA IP Core Device Family Support 1.3.2. 25G Ethernet Intel FPGA IP Core Device Speed Grade Support
1.4. IP Core Verification x
1.4.1. Simulation Environment 1.4.2. Compilation Checking 1.4.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the Intel® Stratix® 10 IP Core Parameters and Options 2.3. Simulating the IP Core 2.4. Generated File Structure 2.5. Integrating Your IP Core in Your Design 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Adding the External Time-of-Day Module for Variations with 1588 PTP Feature 2.5.4. Placement Settings for the 25G Ethernet Intel FPGA IP Core
4. Functional Description x
4.1. 25G Ethernet Intel FPGA IP Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. 25G Ethernet Intel FPGA IP Core Functional Description x
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath 4.1.2. 25 GbE TX PCS 4.1.3. TX RS-FEC 4.1.4. 25G Ethernet Intel FPGA IP Core RX MAC Datapath 4.1.5. Link Fault Signaling Interface 4.1.6. 25 GbE RX PCS 4.1.7. RX RS-FEC 4.1.8. Flow Control 4.1.9. 1588 Precision Time Protocol Interfaces
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion 4.1.1.4. Frame Check Sequence (CRC32) Insertion
4.1.4. 25G Ethernet Intel FPGA IP Core RX MAC Datapath x
4.1.4.1. IP Core Preamble Processing 4.1.4.2. IP Core Malformed Packet Handling 4.1.4.3. Length/Type Field Processing 4.1.4.4. RX CRC Checking and Dynamic Forwarding
4.1.4.3. Length/Type Field Processing x
4.1.4.3.1. Length Checking
4.1.8. Flow Control x
4.1.8.1. TX Pause/PFC Flow Control Frame Transmission Request 4.1.8.2. XON/XOFF Pause Frames
4.1.9. 1588 Precision Time Protocol Interfaces x
4.1.9.1. Implementing a 1588 System That Includes a 25G Ethernet Intel FPGA IP Core 4.1.9.2. PTP Transmit Functionality 4.1.9.3. PTP Receive Functionality 4.1.9.4. External Time-of-Day Module for 1588 PTP Variations 4.1.9.5. PTP Timestamp and TOD Formats 4.1.9.6. Design Considerations in PTP
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers 6.4. Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. PHY Interface Signals 6.7. 1588 PTP Interface Signals 6.8. Miscellaneous Status and Debug Signals 6.9. Reset Signals
6.4. Transceiver Reconfiguration Signals x
6.4.1. Accessing the Native PHY Registers in H-Tile Devices 6.4.2. Accessing the Native PHY Registers in L-Tile Devices
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control Registers 7.5. Statistics Registers 7.6. 1588 PTP Registers 7.7. TX Reed-Solomon FEC Registers 7.8. RX Reed-Solomon FEC Registers
7.5. Statistics Registers x
7.5.1. TX Statistics Registers 7.5.2. RX Statistics Registers
8. Debugging the Link x
8.1. Error Insertion Test and Debugging
1. About the 25G Ethernet Intel FPGA IP
2. Getting Started
3. 25G Ethernet Intel FPGA IP Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide Archives
10. Document Revision History for the 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide

10. Document Revision History for the 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2021.09.15 21.1 19.4.0 Removed references to ncsim
2021.03.29 21.1 19.4.0 Updated the descriptions for the following signals in Table: Signals of the 1588 Precision Time Protocol Interface:
  • tx_etstamp_ins_ctrl_residence_time_calc_format
  • tx_egress_timestamp_64b_data[63:0]
  • tx_egress_timestamp_96b_fingerprint[(W–1):0]
  • tx_egress_timestamp_64b_fingerprint[(W–1):0]
2021.01.29 20.3 19.4.0 Updated the descriptions for the following signals in Table: Signals of the PHY Interface:
  • tx_clkout
  • tx_clkout2
  • rx_clkout
  • rx_clkout2
2020.10.12 20.3 19.4.0
  • Added a note to the Length Checking section to state that the MAC has a counter limit of 0xFFFF starting from Intel® Quartus® Prime Pro Edition software version 20.3 onward.
  • Added a note to the Transceivers section to state that the Intel® Stratix® 10 devices use the OSC_CLK_1 pin to provide the transceiver calibration clock source.
  • Made editorial updates throughout the document.
2020.07.29 20.1 19.4.0 Added the channel_reset signal to Table: Reset Signals.
2020.06.22 20.1 19.4.0
  • Added a new section—Accessing the Native PHY Registers in L-Tile Devices.
  • Renamed section title Disabling Background Calibration to Accessing the Native PHY Registers in H-Tile Devices.
  • Updated the Length/Type Field Processing section.
  • Update the descriptions to the following signals in Table: Avalon® Streaming TX Datapath:
    • l1_tx_data[63:0]
    • l1_tx_valid
    • l1_tx_ready
  • Removed Figure: Client to 25G Ethernet Intel FPGA IP MAC Avalon Streaming Interface.
  • Added the following Figures:
    • Client to 25G Ethernet Intel FPGA IP MAC Avalon® Streaming Interface when Ready Latency is 0 (1 of 2)
    • Client to 25G Ethernet Intel FPGA IP MAC Avalon® Streaming Interface when Ready Latency is 0 (2 of 2)
    • Client to 25G Ethernet Intel FPGA IP MAC Avalon® Streaming Interface when Ready Latency is 3 (1 of 2)
    • Client to 25G Ethernet Intel FPGA IP MAC Avalon® Streaming Interface when Ready Latency is 3 (2 of 2)
2020.04.13 20.1 19.4.0
  • Added a new Table: IP Core Round Trip Latency.
  • Updated the following tables:
    • IP Core FPGA Resource Utilization for 25G Ethernet Intel FPGA IP Core with MAC+PCS+PMA Core Variant for Intel® Stratix® 10 Devices.
    • IP Core FPGA Resource Utilization for 25G Ethernet Intel FPGA IP Core with MAC+PCS Core Variant for Intel® Stratix® 10 Devices.
  • Updated the Simulating the IP Core section.
  • Updated the Length Checking section.
  • Updated the description for l1_rx_error[5:0] Table: Avalon® Streaming RX Datapath.
  • Updated the descriptions for CNTR_RX_1519toMAXB_HI, CNTR_RX_OVERSIZE_LO, and CNTR_RX_OVERSIZE_HI Table: Receive Side Statistics Registers.
  • Updated the description for latency_sclk in Table: Signals of the 1588 Precision Time Protocol Interface.
  • Updated the descriptions for tx_control_phy[1:0] and rx_control_phy[1:0] in Table: Signals of the PHY Interface.
  • Added a note to the description of PHY_TLKIT_ACCESS in Table: PHY Registers.
2020.02.21 19.4 19.4.0
  • Updated the description for frame monitoring and statistics in the 25G Ethernet Intel FPGA IP Core Supported Features section.
  • Updated the Debugging the Link section.
2019.12.16 19.4 19.4.0
  • Updated the description in the About the 25G Ethernet Intel FPGA IP Core section.
  • Updated the description for debug and testability features in the 25G Ethernet Intel FPGA IP Core Supported Features section.
  • Updated the following tables:
    • IP Core FPGA Resource Utilization for 25G Ethernet Intel FPGA IP Core with MAC+PCS+PMA Core Variant for Intel® Stratix® 10 Devices.
    • IP Core FPGA Resource Utilization for 25G Ethernet Intel FPGA IP Core with MAC+PCS Core Variant for Intel® Stratix® 10 Devices.
  • Updated the description in the PTP Transmit Functionality section.
  • Updated the descriptions for the following signals in Table: Signals of the 1588 Precision Time Protocol Interface:
    • tx_etstamp_ins_ctrl_offset_timestamp[15:0]
    • tx_etstamp_ins_ctrl_offset_correction_field[15:0]
    • tx_etstamp_ins_ctrl_offset_checksum_field[15:0]
    • tx_etstamp_ins_ctrl_offset_checksum_correction[15:0]
  • Added rx_am_lock to Table: Miscellaneous Status and Debug Signals.
  • Updated the description and reset value for RXMAC_CONTROL and description for LINK_FAULT in Table: RX MAC Registers.
  • Added reset_status signal to Table: Avalon® Memory-Mapped Management Interface.
  • Updated the Avalon® Memory-Mapped Management Interface section.
  • Updated the Statistics Registers section.
  • Updated for latest Intel® branding standards.
2019.10.11 19.3 19.3.0
  • Updated the description in the About the 25G Ethernet Intel FPGA IP Core section.
  • Updated the PHY feature description in the 25G Ethernet Intel FPGA IP Core Supported Features section.
  • Updated the description in the Hardware Testing section.
  • Updated the description for 0x800, 0x801, 0x802, 0x803, 0x804, 0x805, 0x834, and 0x835 in Table: Transmit Side Statistics Registers.
  • Updated the descriptions for rx_block_lock and rx_pcs_ready in Table: Miscellaneous Status and Debug Signals.
2019.08.29 19.2 19.2.0
  • Added PHY_TLKIT_ACCESS register to Table: PHY Registers.
  • Updated the description for CNTR_RX_RUNT_LO and CNTR_RX_RUNT_HI in Table: Receive Side Statistics Registers.
  • Updated the l2_rxstatus_data bits to l1_rxstatus_data bits in the Length/Type Field Processing section.
  • Updated l2_rx_error[2], l2_rx_error[3], and l2_rx_error[4] to l1_rx_error[2], l1_rx_error[3], and l1_rx_error[4] in the Length Checking section.
  • Updated the steps in the Disabling Background Calibration section.
Document Version Intel® Quartus® Prime Version Changes
2019.04.05 19.1
  • Added a new IP core parameter—Enable auto adaptation triggering for RX PMA CTLE/DFE mode.
  • Added a new Topic: Disabling Background Calibration.
  • Updated the 25G Ethernet Intel FPGA IP Core Supported Features to state support for adaptive mode for RX PMA Adaptation.
  • Renamed Altera Debug Master Endpoint (ADME) to Native PHY Debug Master Endpoint (NPDME).
  • Updated the Adding the Transceiver PLL topic.
  • Updated the Placement Settings for the 25G Ethernet Intel FPGA IP Core topic.
  • Updated the Flow Control topic.
  • Updated the XON/XOFF Pause Frames topic.
  • Updated the Transceivers topic.
  • Updated the second note in the Control, Status, and Statistics Register Descriptions topic.
  • Updated the following Tables:
    • Updated Table: Supported Device Speed Grades to update the second footnote for Intel® Stratix® 10 L- and H-tile device family.
    • Updated Table: IP Core FPGA Resource Utilization for 25G Ethernet Intel FPGA IP Core with MAC+PCS+PMA Core Variant for Intel® Stratix® 10 Devices.
    • Updated Table: IP Core FPGA Resource Utilization for 25G Ethernet Intel FPGA IP Core with MAC+PCS Core Variant for Intel® Stratix® 10 Devices.
    • Updated Table: Transceiver Signals to update the direction values for tx_serial_clk0 and tx_serial_clk1.
  • Made minor topic restructuring to the Core Functional Description section.
  • Made editorial updates throughout the document.
2019.01.02 18.1
  • Removed the reference to Intel Stratix 10 E-tile devices because 25G Ethernet Intel FPGA IP core supports Intel Stratix 10 H-tile and L-tile devices only.
  • Updated Table: Supported Device Speed Grades to add a footnote to clarify that Intel® Stratix® 10 devices with both E- and H-tile transceivers are supported if the IP core is only utilizing the H-tile transceiver.
  • Added a note to Control, Status, and Statistics Register Descriptions topic.
2018.10.05 18.1 Updated Table: PHY Registers to correct the bit[1] description for RX_PCS_FULLY_ALIGNED_S.
2018.10.03 18.1
  • Added a new feature—Elective PMA.
  • Added a new signal for 1588 Precision Time Protocol Interface—latency_sclk.
  • Updated the About the 25G Ethernet Intel FPGA IP Core topic:
    • Updated notes in the topic.
    • Updated Figure title 25G Ethernet Intel FPGA IP MAC IP Clock Diagram to 25G Ethernet MAC, PCS, and PMA IP Clock Diagram.
    • Updated Figure title 10G/25G Ethernet MAC IP Clock Diagram to 10G/25G Ethernet MAC, PCS, and PMA IP Clock Diagram.
    • Added new Figures:
      • 25G Ethernet MAC and PCS IP Clock Diagram.
      • 10G/25G Ethernet MAC and PCS IP Clock Diagram.
    • Updated Table: IP Core Parameters to include Core Variants parameter.
    • Added new topic: PHY Interface Signals.
    • Updated Figure: 25G Ethernet Intel FPGA IP Signals and Interfaces to include PHY interface signals.
  • Updated the Performance and Resource Utilization topic:
    • Added new Tables:
      • IP Core Variation Encoding for Resource Utilization for MAC+PCS Core Variant.
      • IP Core FPGA Resource Utilization for 25G Ethernet Intel FPGA IP Core with MAC+PCS Core Variant for Intel Stratix 10 Devices.
    • Updated Table title IP Core Variation Encoding for Resource Utilization to IP Core Variation Encoding for Resource Utilization for MAC+PCS+PMA Core Variant.
    • Updated Table title IP Core FPGA Resource Utilization for 25G Ethernet Intel FPGA IP Core for Intel Stratix 10 Devices to IP Core FPGA Resource Utilization for 25G Ethernet Intel FPGA IP Core with MAC+PCS+PMA Core Variant for Intel Stratix 10 Devices.
    • Updated Table: IP Core Parameters to update the description for Enable flow control.
  • Updated the descriptions of the following topics:
    • Flow Control
    • XON/XOFF Pause Frames
  • Updated the Installing and Licensing Intel FPGA IP Cores topic to remove Intel Quartus Prime Standard Edition software references.
  • Updated the following Tables:
    • Updated Table: Supported Device Speed Grades:
      • Updated Table title Slowest Supported Device Speed Grades to Supported Device Speed Grades.
      • Updated the Intel Stratix 10 device family to include L-tile, H-tile, and E-tile support.
      • Added a footnote for Intel Stratix 10 device family to state that only Intel Stratix 10 devices ending with "VG", VGS3", and "LG" suffixes in the part number are supported.
    • Updated Table: 25G Ethernet Intel FPGA IP Core Current Release Information.
    • Updated Table: IP Core Generated Files to remove <your_ip>.debuginfo filename.
    • Updated Table: PHY Registers:
      • Added bit[1] description for RX_PCS_FULLY_ALIGNED_S.
      • Updated the descriptions for KHZ_RX and KHZ_TX.
  • Updated the following Figures:
    • Updated Figure: IP Core Generated Files
    • Updated Figure: 25G Ethernet Intel FPGA IP Core with MAC, PCS, and PMA Clock Diagram
    • Updated Figure: High Level Block Diagram of the TX PCS with Optional RS-FEC Datapath.:
      • Updated figure to include RS-FEC block.
      • Updated figure title from High Level Block Diagram of the Soft TX PCS to High Level Block Diagram of the TX PCS with Optional RS-FEC Datapath.
      • Updated Figure: High Level Block Diagram of the RX PCS with Optional RS-FEC Datapath.:
        • Updated figure to include RS-FEC block.
        • Updated figure title from High Level Block Diagram of the Soft RX PCS to High Level Block Diagram of the RX PCS with Optional RS-FEC Datapath.
  • Made editorial updates throughout the document.
2018.07.17 18.0
  • Updated Table: TX 1588 PTP Registers to correct the HW reset value of the TX_PTP_CLK_Period register to 0x28F5C.
  • Updated Table: RX 1588 PTP Registers to update the description and correct the HW reset value of the RX_PTP_CLK_Period register to 0x28F5C.
2018.06.06 18.0 Initial release.
Level Two Title