25G Ethernet Intel® Stratix® 10 FPGA IP User Guide

ID 683154
Date 9/15/2021
Public
Document Table of Contents

4.2.2. Bit Order For TX and RX Datapaths

The TX bit order matches the placement shown in the PCS lanes as illustrated in IEEE Standard for Ethernet, Section 4, Figure 49-5. The RX bit order matches the placement shown in IEEE Standard for Ethernet, Section 4, Figure 49-6.

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