25G Ethernet Intel® Stratix® 10 FPGA IP User Guide

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ID 683154
Date 3/29/2021
Public
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6.4.1. Accessing the Native PHY Registers in H-Tile Devices

For Intel® Stratix® 10 H-tile production devices, disable the background calibration first prior to accessing the transceiver core reconfiguration register. The Intel® Stratix® 10 H-tile ES devices do not have background calibration.

In Intel® Quartus® Prime software version 19.2 onwards, use the following steps to access the transceiver core reconfiguration registers:

  1. Write 0x1 into register 0x343[0] of the Avalon® memory-mapped control and status interface to hold the auto adaptation module in an Idle state. If you have disabled the Enable auto adaptation triggering for RX PMA CTLE/DFE mode parameter, you can skip this step.
  2. Write 0x0 into register 0x542[0] of the transceiver control and status registers using the transceiver reconfiguration Avalon® memory-mapped interface to disable background calibration.
  3. Access the transceiver register, for example, to perform the transceiver reconfiguration.
  4. Once completed, write 0x1 into register 0x542[0] of the transceiver control and status registers using the transceiver reconfiguration Avalon® memory-mapped interface to enable background calibration.
  5. Write 0x0 into register 0x343[0] of the Avalon® memory-mapped control and status interface to release the auto adaptation module from the Idle state. If you have disabled the Enable auto adaptation triggering for RX PMA CTLE/DFE mode parameter, you can skip this step.
Note: If you do not select the Enable auto adaptation triggering for RX PMA CTLE/DFE mode parameter, refer to Adaptation Control - Start section of the Intel® Stratix® 10 L- and H-Tile Transceiver PHY User Guide for more information about how to start adaptation.

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