1. About the 25G Ethernet Intel FPGA IP 2. Getting Started 3. 25G Ethernet Intel FPGA IP Parameters 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Debugging the Link 9. 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide Archives 10. Document Revision History for the 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers 6.4. Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. PHY Interface Signals 6.7. 1588 PTP Interface Signals 6.8. Miscellaneous Status and Debug Signals 6.9. Reset Signals
4.1.8. Flow Control
Flow control reduces congestion at the local or remote link partner. When either link partner experiences congestion, the respective transmit control sends pause frames. XOFF Pause frames stop the remote transmitter. XON Pause frames let the remote transmitter resume data transmission. The 25G Ethernet Intel FPGA IP core supports both standard and Priority-based Flow Control (PFC) control frames.
Figure 21. Flow Control Module Conceptual OverviewThe flow control module acts as a buffer between client logic and the TX and RX MAC.
Standard Flow Control (Pause Frame Flow Control):
- Inhibits the next client frame transmission on the reception of a valid Pause frame.
Priority-based Flow Control (PFC):
- PFC frame transmission follows a priority-based arbitration scheme, where the Frame Type indication is provided for the usage of external downstream logic.
- Inhibits the per queue client frame transmission on the reception of a valid PFC frame from the client. Includes per-queue PFC Pause quanta duration indicator
Flow Control includes the following features:
|Feature||Standard Flow Control||Priority-based Flow Control (PFC)|
|Generation and Transmission|
|Programmable 1-bit or 2-bit XON/XOFF request mode||Supported||Supported|
|In 2-bit request mode, programmable selection of register or signal-based control||Supported||Supported|
|Programmable destination and source addresses||Supported||Supported|
|Programmable pause quanta||Supported||Supported|
|Programmable per-queue XOFF frame separation||—||Supported|
|Reception and Decode|
|Programmable destination address for filtering incoming pause and PFC frames||Supported||Supported|
|Configurable enable, directing the IP core to ignore incoming flow control frames||Supported||Supported|
|Per-queue client frame transmission pause duration indicator||—||Supported|
The 25G Ethernet Intel FPGA IP core supports the flow control feature for either value of the Ready Latency parameter. However, in standard flow control you might experience data delay if you select the value of 3 for this parameter. The IP core might still hold user data packet in its internal buffer if transmission of the IP core stops due to flow control. This issue does not occur in priority-based flow control.
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