25G Ethernet Intel® Stratix® 10 FPGA IP User Guide

ID 683154
Date 9/15/2021
Public
Document Table of Contents

4.1.9.1. Implementing a 1588 System That Includes a 25G Ethernet Intel FPGA IP Core

The 1588 specification in IEEE 1588-2008 Precision Clock Synchronization Protocol for Networked Measurement and Control Systems Standard describes various systems you can implement in hardware and software to synchronize clocks in a distributed system by communicating offset and frequency correction information between master and slave clocks in arbitrarily complex systems. A 1588 system that includes the 25G Ethernet Intel FPGA IP core with 1588 PTP functionality uses the incoming and outgoing timestamp information from the IP core and the other modules in the system to synchronize clocks across the system.

The 25G Ethernet Intel FPGA IP core with 1588 PTP functionality provides the timestamp manipulation and basic update capabilities required to integrate your IP core in a 1588 system. You can specify that packets are PTP packets, and how the IP core should update incoming timestamps from the client interface before transmitting them on the Ethernet link. The IP core does not implement the event messaging layers of the protocol, but rather provides the basic hardware capabilities that support a system in implementing the full 1588 protocol.

Figure 22. Example Ethernet System with Ordinary Clock Master and Ordinary Clock SlaveYou can implement both master and slave clocks using the 25G Ethernet Intel FPGA IP core with 1588 PTP functionality. Refer to Adding the External Time-of-Day Module for Variations with 1588 PTP Feature for implementation of the TOD module.
Figure 23. Hardware Configuration Example Using 25G Ethernet Intel FPGA IP core in a 1588 System in Transparent Clock ModeRefer to Adding the External Time-of-Day Module for Variations with 1588 PTP Feature for implementation of the TOD module.
Figure 24. Software Flow Using Transparent Clock Mode SystemThis figure from the 1588 standard is augmented with the timestamp labels shown in the transparent clock system figure. A precise description of the software requirements is beyond the scope of this document. Refer to the 1588 standard.
Figure 25. Example Boundary Clock with One Slave Port and Two Master PortsYou can implement a 1588 system in boundary clock mode using the 25G Ethernet Intel FPGA IP core with 1588 PTP functionality. Refer to Adding the External Time-of-Day Module for Variations with 1588 PTP Feature for implementation of the TOD module.

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