1. About the DIB Intel® Stratix® 10 FPGA IP User Guide 2. About the DIB Intel® Stratix® 10 FPGA IP 3. Functional Description 4. Creating and Parameterizing the Intel FPGA IP 5. Designing with the DIB Intel® Stratix® 10 FPGA IP 6. DIB Intel® Stratix® 10 FPGA IP Interface 7. DIB Intel® Stratix® 10 FPGA IP Parameters 8. Document Revision History for the DIB Intel® Stratix® 10 FPGA IP User Guide A. Die-to-Die Mapping B. Example Pin Locations for One DIB Channel
1. About the DIB Intel® Stratix® 10 FPGA IP User Guide
|Intel® Quartus® Prime Design Suite 20.2
|IP Version 19.3.0
This user guide provides the features, architecture description, steps to instantiate, and guidelines to design the DIB Intel® Stratix® 10 FPGA IP, specifically for Intel® Stratix® 10 GX 1SG10M variant.
This document is intended for:
- Design architect to make IP selection during system level design planning phase
- Hardware designers when integrating the IP into their system level design
- Validation engineers during system level simulation and hardware validation phase
The following table lists other reference documents which are related to the DIB Interface Intel® Stratix® 10 IP.
|Intel® Stratix® 10 GX/SX Device Overview
|Provides information about Intel® Stratix® 10 GX 10M variant.
|Intel® Stratix® 10 Device Data Sheet
|Provides information about the electrical characteristics, switching characteristics, configuration specifications, and timing for Intel® Stratix® 10 devices.
|Direct Interface Bus (DIB) Intel® Stratix® 10 FPGA IP Release Notes
|Lists the changes made in a particular release.
Acronyms and Glossary
|Direct Interface Bus
|Device under test
|Time-division multiplexing (TMD)
|Method of transmitting multiple data signals over one channel in a series of time slots.