Direct Interface Bus (DIB) Intel® Stratix® 10 FPGA IP User Guide

ID 683142
Date 3/18/2021
Public
Document Table of Contents

1. About the DIB Intel® Stratix® 10 FPGA IP User Guide

Updated for:
Intel® Quartus® Prime Design Suite 20.2
IP Version 19.3.0

This user guide provides the features, architecture description, steps to instantiate, and guidelines to design the DIB Intel® Stratix® 10 FPGA IP, specifically for Intel® Stratix® 10 GX 1SG10M variant.

Intended Audience

This document is intended for:

  • Design architect to make IP selection during system level design planning phase
  • Hardware designers when integrating the IP into their system level design
  • Validation engineers during system level simulation and hardware validation phase

Related Documents

The following table lists other reference documents which are related to the DIB Interface Intel® Stratix® 10 IP.
Table 1.  Related Documents
Reference Description
Intel® Stratix® 10 GX/SX Device Overview Provides information about Intel® Stratix® 10 GX 10M variant.
Intel® Stratix® 10 Device Data Sheet Provides information about the electrical characteristics, switching characteristics, configuration specifications, and timing for Intel® Stratix® 10 devices.
Direct Interface Bus (DIB) Intel® Stratix® 10 FPGA IP Release Notes Lists the changes made in a particular release.

Acronyms and Glossary

Table 2.  Acronym List
Acronym Expansion
DIB Direct Interface Bus
DUT Device under test
TDM Time-division multiplexing
TX Transmitter
RX Receiver
Table 3.  Glossary List
Term Description
Time-division multiplexing (TMD) Method of transmitting multiple data signals over one channel in a series of time slots.

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