Direct Interface Bus (DIB) Intel® Stratix® 10 FPGA IP User Guide

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ID 683142
Date 3/18/2021
Public
Document Table of Contents
Document Table of Contents
1. About the DIB Intel® Stratix® 10 FPGA IP User Guide 2. About the DIB Intel® Stratix® 10 FPGA IP 3. Functional Description 4. Creating and Parameterizing the Intel FPGA IP 5. Designing with the DIB Intel® Stratix® 10 FPGA IP 6. DIB Intel® Stratix® 10 FPGA IP Interface 7. DIB Intel® Stratix® 10 FPGA IP Parameters 8. Document Revision History for the DIB Intel® Stratix® 10 FPGA IP User Guide A. Die-to-Die Mapping B. Example Pin Locations for One DIB Channel
2. About the DIB Intel® Stratix® 10 FPGA IP
2.1. Release Information 2.2. Device Support for DIB Intel® Stratix® 10 FPGA IP 2.3. DIB Intel® Stratix® 10 FPGA IP Features 2.4. Latency
3. Functional Description
3.1. Bypass Mode 3.2. Asynchronous Mode 3.3. Synchronous Mode
3.1. Bypass Mode
3.1.1. AUX Channel Settings
4. Creating and Parameterizing the Intel FPGA IP
4.1. IP Catalog and Parameter Editor 4.2. Creating a New Intel® Quartus® Prime Project 4.3. Parameterizing and Generating the IP 4.4. Compiling the DIB Intel® Stratix® 10 FPGA IP Design 4.5. Programming an FPGA Device
5. Designing with the DIB Intel® Stratix® 10 FPGA IP
5.1. Reset Architecture 5.2. Clocking in Asynchronous and Synchronous Modes 5.3. Timing Closure 5.4. Setting Bypass, Asynchronous, and Synchronous Modes in One DIB Instance
5.2. Clocking in Asynchronous and Synchronous Modes
5.2.1. Clocking Options 5.2.2. Clock Synchronization
5.3. Timing Closure
5.3.1. Timing Transfer for Bypass Mode 5.3.2. Timing Transfer for TDM Modes
6. DIB Intel® Stratix® 10 FPGA IP Interface
6.1. DIB Intel® Stratix® 10 FPGA IP Clocks 6.2. DIB Intel® Stratix® 10 FPGA IP User Interface Signals
1. About the DIB Intel® Stratix® 10 FPGA IP User Guide
2. About the DIB Intel® Stratix® 10 FPGA IP
3. Functional Description
4. Creating and Parameterizing the Intel FPGA IP
5. Designing with the DIB Intel® Stratix® 10 FPGA IP
6. DIB Intel® Stratix® 10 FPGA IP Interface
7. DIB Intel® Stratix® 10 FPGA IP Parameters
8. Document Revision History for the DIB Intel® Stratix® 10 FPGA IP User Guide
A. Die-to-Die Mapping
B. Example Pin Locations for One DIB Channel

1. About the DIB Intel® Stratix® 10 FPGA IP User Guide

Updated for:
Intel® Quartus® Prime Design Suite 20.2
IP Version 19.3.0

This user guide provides the features, architecture description, steps to instantiate, and guidelines to design the DIB Intel® Stratix® 10 FPGA IP, specifically for Intel® Stratix® 10 GX 1SG10M variant.

Intended Audience

This document is intended for:

  • Design architect to make IP selection during system level design planning phase
  • Hardware designers when integrating the IP into their system level design
  • Validation engineers during system level simulation and hardware validation phase

Related Documents

The following table lists other reference documents which are related to the DIB Interface Intel® Stratix® 10 IP.
Table 1.  Related Documents
Reference Description
Intel® Stratix® 10 GX/SX Device Overview Provides information about Intel® Stratix® 10 GX 10M variant.
Intel® Stratix® 10 Device Data Sheet Provides information about the electrical characteristics, switching characteristics, configuration specifications, and timing for Intel® Stratix® 10 devices.
Direct Interface Bus (DIB) Intel® Stratix® 10 FPGA IP Release Notes Lists the changes made in a particular release.

Acronyms and Glossary

Table 2.  Acronym List
Acronym Expansion
DIB Direct Interface Bus
DUT Device under test
TDM Time-division multiplexing
TX Transmitter
RX Receiver
Table 3.  Glossary List
Term Description
Time-division multiplexing (TMD) Method of transmitting multiple data signals over one channel in a series of time slots.
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