Direct Interface Bus (DIB) Intel® Stratix® 10 FPGA IP User Guide

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ID 683142
Date 3/18/2021
Public
Document Table of Contents

3. Functional Description

The DIB Intel® Stratix® 10 FPGA IP provides three direct interface bus subsystems per Intel® Stratix® 10 GX 10M die.

Every DIB subsystem contains 24 standard channels, and the bypass operation mode also contains an extra AUX channel. Each channel has four banks, and each bank contains 22 or 20 usable I/Os, depending on the mode of the operation.

The DIB Intel® Stratix® 10 FPGA IP provides three modes of operation for each DIB channel instance:
  • Bypass Mode
  • Synchronous Mode
  • Asynchronous Mode
Figure 1. DIB Intel® Stratix® 10 FPGA IP Interface Connections
Figure 2. DIB Subsystem (24 Standard Channels and 1 AUX Channel)
Figure 3. Single DIB Channel

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