1. About the DIB Intel® Stratix® 10 FPGA IP User Guide 2. About the DIB Intel® Stratix® 10 FPGA IP 3. Functional Description 4. Creating and Parameterizing the Intel FPGA IP 5. Designing with the DIB Intel® Stratix® 10 FPGA IP 6. DIB Intel® Stratix® 10 FPGA IP Interface 7. DIB Intel® Stratix® 10 FPGA IP Parameters 8. Document Revision History for the DIB Intel® Stratix® 10 FPGA IP User Guide A. Die-to-Die Mapping B. Example Pin Locations for One DIB Channel
3.2. Asynchronous Mode
In Asynchronous mode, the DIB uses the hard TDM provided by the IP.
The Asynchronous mode includes the following features:
- Use this mode when 1:1, 2:1, or 4:1 TDM multiplexing is required and no soft TDM logic is required.
- System clock is not used.
- The DIB clock and DUT clock have a synchronous relationship.
- You may use your own asynchronous DUT clock, but the dut_clk input to a DIB instance must be connected to a clock of the ratio selected in the parameter editor.
- The DIB subsystem TDM block always ensures that all RX ports (four ports from 4:1 TDM, two ports from 2:1 TDM, or single port from 1:1 TDM) are available to be sampled in the next system clock (or DUT clock) on the RX side.
- The DIB TDM multiplexer halts the multiplexer select at the last data input until all data are sampled at the RX system clock.
- When the data sampling is complete, the multiplexer select rolls back to the initial location for a new phase of data on the TX side.
- You can connect the DIB clock to the DUT flip flops only in an asynchronous manner.
Figure 7. Asynchronous Mode Setup
Figure 8. Asynchronous Mode Timing Diagram
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