Direct Interface Bus (DIB) Intel® Stratix® 10 FPGA IP User Guide

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ID 683142
Date 3/18/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the DIB Intel® Stratix® 10 FPGA IP User Guide 2. About the DIB Intel® Stratix® 10 FPGA IP 3. Functional Description 4. Creating and Parameterizing the Intel FPGA IP 5. Designing with the DIB Intel® Stratix® 10 FPGA IP 6. DIB Intel® Stratix® 10 FPGA IP Interface 7. DIB Intel® Stratix® 10 FPGA IP Parameters 8. Document Revision History for the DIB Intel® Stratix® 10 FPGA IP User Guide A. Die-to-Die Mapping B. Example Pin Locations for One DIB Channel
2. About the DIB Intel® Stratix® 10 FPGA IP x
2.1. Release Information 2.2. Device Support for DIB Intel® Stratix® 10 FPGA IP 2.3. DIB Intel® Stratix® 10 FPGA IP Features 2.4. Latency
3. Functional Description x
3.1. Bypass Mode 3.2. Asynchronous Mode 3.3. Synchronous Mode
3.1. Bypass Mode x
3.1.1. AUX Channel Settings
4. Creating and Parameterizing the Intel FPGA IP x
4.1. IP Catalog and Parameter Editor 4.2. Creating a New Intel® Quartus® Prime Project 4.3. Parameterizing and Generating the IP 4.4. Compiling the DIB Intel® Stratix® 10 FPGA IP Design 4.5. Programming an FPGA Device
5. Designing with the DIB Intel® Stratix® 10 FPGA IP x
5.1. Reset Architecture 5.2. Clocking in Asynchronous and Synchronous Modes 5.3. Timing Closure 5.4. Setting Bypass, Asynchronous, and Synchronous Modes in One DIB Instance
5.2. Clocking in Asynchronous and Synchronous Modes x
5.2.1. Clocking Options 5.2.2. Clock Synchronization
5.3. Timing Closure x
5.3.1. Timing Transfer for Bypass Mode 5.3.2. Timing Transfer for TDM Modes
6. DIB Intel® Stratix® 10 FPGA IP Interface x
6.1. DIB Intel® Stratix® 10 FPGA IP Clocks 6.2. DIB Intel® Stratix® 10 FPGA IP User Interface Signals
1. About the DIB Intel® Stratix® 10 FPGA IP User Guide
2. About the DIB Intel® Stratix® 10 FPGA IP
3. Functional Description
4. Creating and Parameterizing the Intel FPGA IP
5. Designing with the DIB Intel® Stratix® 10 FPGA IP
6. DIB Intel® Stratix® 10 FPGA IP Interface
7. DIB Intel® Stratix® 10 FPGA IP Parameters
8. Document Revision History for the DIB Intel® Stratix® 10 FPGA IP User Guide
A. Die-to-Die Mapping
B. Example Pin Locations for One DIB Channel

7. DIB Intel® Stratix® 10 FPGA IP Parameters

Use the DIB Intel® Stratix® 10 FPGA IP parameter editor to configure your design.
Table 14.  General Tab Parameters

Parameter

Value

Description

Speed grade

–

Speed grade of the selected Intel® Stratix® 10 GX 10M variant (1SG10M). The software automatically sets the speed grade based on the selected variant.

DIB Channel Type
  • Standard Channel
  • AUX Channel
Select the desired channel.
  • Standard Channel: Available in all three modes.
  • AUX Channel: Available in bypass mode.
Enable DIB bank 0–3

On, Off

 Turn on to enable a bank.
Synchronization Mode
  • Synchronous
  • Asynchronous
 Select the desired TDM mode.
  • Synchronous: Select this mode when you want to use soft TDM.
  • Asynchronous: Select this mode when you want to use hard TDM.
DIB to System Clock Ratio

1, 2, 4

Available only when you select Synchronous mode.

Select the DIB clock to system clock ratio for soft TDM.

Reduce Sync Mode P2C Latency

On, Off

Available only when you select Synchronous mode.

When you turn this parameter, the IP removes the periphery-to-core register stage (driven by the divided clock), However, the removal of this stage may cause increase in timing closure effort.

DIB to DUT Clock Ratio

8, 10, 20, 25, 40, 50, 100, 200

Available only when you select Asynchronous mode.

Select the DIB clock to DUT clock ratio for hard TDM.

Table 15.  Banks 0–3 Tab Parameters

Parameter

Value

Description

PHY Mode

  • Bypass (1:1)
  • TDM 1:1
  • TDM 2:1
  • TDM 4:1

Select the PHY mode you want for the selected bank.

Min output delay

Variable

Available only when you select Bypass (1:1) mode.

Set the minimum and maximum delay for the paired output bank in the remote die.

Max output delay

Variable

I/O Mode
  • Input
  • Output
Select the I/O direction mode for the selected bank.
    • Input: RX mode
    • Output: TX mode
Table 16.  Diagnostics Tab Parameters

Parameter

Value

Description

DIB Clock Frequency

0.1–400 MHz

Set the clock frequency of the DIB subsystem.

System Clock Frequency

0.1–400 MHz

Available only when a bank is in Synchronous TDM mode.

Set the system clock frequency.
Use recommended DUT clock frequency

On, Off
  • Turn on to allow the IP to automatically calculate the DUT clock frequency.
  • Turn off if you want to specify your own DUT clock frequency.
DUT Clock Frequency

0.1–100 MHz

Available only when a bank is in Bypass or Asynchronous TDM mode.

Set the DUT clock frequency.
Use recommended example design PLL reference clock frequency

On, Off
  • Turn on to allow the IP to automatically calculate the PLL reference clock frequency for optimal performance.
  • Turn off if you want to specify your own PLL reference clock frequency.
Reference clock frequency for example design PLL

25.0–100 MHz

Available only for the design example PLL.

Set the PLL reference clock frequency for the PLL that supplies to the DIB clock and system clock.

Table 17.  Example Design Tab Parameters

Parameter

Value

Description

Simulation

On, Off

Turn on this parameter to generate the necessary design simulation files.

Synthesis

On, Off

Turn on this parameter to generate the necessary design synthesis files. Use these files to compile the design in the Intel® Quartus® Prime Pro Editionsoftware for hardware testing.

Generate a second paired channel

On, Off

Turn on this parameter to generate a second design example that pairs with selected settings. The paired channel has reversed I/O settings and flipped bank indices.

Simulation HDL format
  • Verilog
  • VHDL
 Select the format of the RTL files generated for simulating the design example.
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