2. About the DIB Intel® Stratix® 10 FPGA IP
The Intel® Stratix® 10 GX 10M variant has two dies. Each die is configured separately. The connection that the DIB Intel® Stratix® 10 FPGA IP provides between the two dies is statically set at configuration time.
- Each DIB instance must have at least one pin location assigned to allow for other pin locations to be automatically assigned.
- The two dies in a Intel® Stratix® 10 GX 10M variant are identical; die 1 is rotated 180 degrees to die 2.
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