1. About the DIB Intel® Stratix® 10 FPGA IP User Guide 2. About the DIB Intel® Stratix® 10 FPGA IP 3. Functional Description 4. Creating and Parameterizing the Intel FPGA IP 5. Designing with the DIB Intel® Stratix® 10 FPGA IP 6. DIB Intel® Stratix® 10 FPGA IP Interface 7. DIB Intel® Stratix® 10 FPGA IP Parameters 8. Document Revision History for the DIB Intel® Stratix® 10 FPGA IP User Guide A. Die-to-Die Mapping B. Example Pin Locations for One DIB Channel
3.1. Bypass Mode
In Bypass mode, the DIB acts as a wire connection between dies.
The Bypass mode includes the following features:
- The propagation delay between dies is the wire delay.
- The latency between DIB pins is 2.5 ns.
- The directional granularity is at the bank level.
- This mode does not require a DIB clock.
- Use appropriate input or output delay constraints during Intel® Quartus® Prime compilation to accommodate the interface (refer to Timing Transfer for Bypass Mode).
- Enables both standard and AUX channels.
Figure 4. Bypass Mode Block Diagram
Figure 5. Bypass Mode Timing DiagramThe IP treats the connection between the TX die and RX dies as a wire signal. Ensure that the RX DUT clock rising edge (with respect to the TX DUT clock rising edge) accounts for the time delay from the TX side flip flop, across the interface, and to the receiving flip flop.
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