Direct Interface Bus (DIB) Intel® Stratix® 10 FPGA IP User Guide

ID 683142
Date 3/18/2021
Document Table of Contents

5.3. Timing Closure

You must compile each Intel® Stratix® 10 GX 10M die instance in the Intel® Quartus® Prime Pro Edition software separately. Separate compilation means that you must configure the timing closure for each die separately.

Especially in cases when data or clocks are being transferred from one die to another, you may need to use certain budgeting schemes to enable timing closure timing in each die independently. Only then, the timing closure across the two dies is guaranteed.

Consider the following timing transfers to account for the data transfer from the system clock on one die to the system clock on the other die.
  • Timing transfer for Bypass mode:
    • Core to DIB I/O
    • DIB I/O to core
  • Timing transfer for TDM Synchronous and Asynchronous modes:
    • TX die: Core to DIB or Periphery
    • RX die: DIB or Periphery to Core
    • Across dies: TDM to TDM

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