Direct Interface Bus (DIB) Intel® Stratix® 10 FPGA IP User Guide

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ID 683142
Date 3/18/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the DIB Intel® Stratix® 10 FPGA IP User Guide 2. About the DIB Intel® Stratix® 10 FPGA IP 3. Functional Description 4. Creating and Parameterizing the Intel FPGA IP 5. Designing with the DIB Intel® Stratix® 10 FPGA IP 6. DIB Intel® Stratix® 10 FPGA IP Interface 7. DIB Intel® Stratix® 10 FPGA IP Parameters 8. Document Revision History for the DIB Intel® Stratix® 10 FPGA IP User Guide A. Die-to-Die Mapping B. Example Pin Locations for One DIB Channel
2. About the DIB Intel® Stratix® 10 FPGA IP x
2.1. Release Information 2.2. Device Support for DIB Intel® Stratix® 10 FPGA IP 2.3. DIB Intel® Stratix® 10 FPGA IP Features 2.4. Latency
3. Functional Description x
3.1. Bypass Mode 3.2. Asynchronous Mode 3.3. Synchronous Mode
3.1. Bypass Mode x
3.1.1. AUX Channel Settings
4. Creating and Parameterizing the Intel FPGA IP x
4.1. IP Catalog and Parameter Editor 4.2. Creating a New Intel® Quartus® Prime Project 4.3. Parameterizing and Generating the IP 4.4. Compiling the DIB Intel® Stratix® 10 FPGA IP Design 4.5. Programming an FPGA Device
5. Designing with the DIB Intel® Stratix® 10 FPGA IP x
5.1. Reset Architecture 5.2. Clocking in Asynchronous and Synchronous Modes 5.3. Timing Closure 5.4. Setting Bypass, Asynchronous, and Synchronous Modes in One DIB Instance
5.2. Clocking in Asynchronous and Synchronous Modes x
5.2.1. Clocking Options 5.2.2. Clock Synchronization
5.3. Timing Closure x
5.3.1. Timing Transfer for Bypass Mode 5.3.2. Timing Transfer for TDM Modes
6. DIB Intel® Stratix® 10 FPGA IP Interface x
6.1. DIB Intel® Stratix® 10 FPGA IP Clocks 6.2. DIB Intel® Stratix® 10 FPGA IP User Interface Signals
1. About the DIB Intel® Stratix® 10 FPGA IP User Guide
2. About the DIB Intel® Stratix® 10 FPGA IP
3. Functional Description
4. Creating and Parameterizing the Intel FPGA IP
5. Designing with the DIB Intel® Stratix® 10 FPGA IP
6. DIB Intel® Stratix® 10 FPGA IP Interface
7. DIB Intel® Stratix® 10 FPGA IP Parameters
8. Document Revision History for the DIB Intel® Stratix® 10 FPGA IP User Guide
A. Die-to-Die Mapping
B. Example Pin Locations for One DIB Channel

A. Die-to-Die Mapping

The mapping information provides you the details of the placement of I/O banks, channels and subsystems in the dies.
Table 18.  Mapping of DIB Subsystem Indices for A Pair of Dies (Die A to Die B)Rule: I/O Bank X in Die A = I/O Bank (2-X) in Die B
Left Die (A)

Subsystem #

Right Die (B)

Subsystem #

2 0
1 1
0 2
Table 19.  Mapping of DIB Channel Indices Within A Pair of Subsystems from Die A to Die BRule: Channel X in Die A = Channel (23-X) in Die B; AUX channel in Die A = AUX channel in Die B
Left Die (A)

Channel #

Right Die (B)

Channel #

23 0
22 1
21 2
20 3
19 4
18 5
17 6
16 7
15 8
14 9
13 10
12 11
AUX AUX
11 12
10 13
9 14
8 15
7 16
6 17
5 18
4 19
3 20
2 21
1 22
0 23
Table 20.  Mapping of DIB I/O Bank Indices Within A Pair of Channels from Die A to Die BRule: I/O Bank X in Die A = I/O Bank (3-X) in Die B
Left Die (A)

I/O Bank #

Right Die (B)

I/O Bank #

3 0
2 1
1 2
0 3
Table 21.  Mapping of Data Bits Within A Pair of I/O Banks from Die A to Die BRule: Bit X in Die A = Bit X in Die B
Note: Non-mapped bits from the 82-bit RX or TX interface are disconnected or tied off.
Bypass Configuration TDM 2:1 Configuration TDM 4:1 Configuration AUX Channel, Bank 2/1 Configuration 3
Left Die (A)

Data Bit #

Right Die (B)

Data Bit #

Left Die (A)

Data Bit #

Right Die (B)

Data Bit #

Left Die (A)

Data Bit #

Right Die (B)

Data Bit #

Left Die (A)

Data Bit #

Right Die (B)

Data Bit #

0 0 2 2 2 2 0 0
1 1 3 3 3 3 1 1
2 2 4 4 4 4 2 2
3 3 5 5 5 5 3 3
4 4 6 6 6 6 4 4
5 5 7 7 7 7 5 5
6 6 8 8 8 8 6 6
7 7 9 9 9 9 7 7
8 8 10 10 10 10 8 8
9 9 11 11 11 11 9 9
10 10 12 12 12 12 10 10
11 11 13 13 13 13 11 11
12 12 14 14 14 14 12 12
13 13 15 15 15 15 13 13
14 14 16 16 16 16 14 14
15 15 17 17 17 17 15 15
16 16 18 18 18 18    
17 17 19 19 19 19
18 18 20 20 20 20
19 19 21 21 21 21
20 20 22 22 22 22
21 21 23 23 23 23
    24 24 24 24
25 25 25 25
26 26 26 26
27 27 27 27
28 28 28 28
29 29 29 29
30 30 30 30
31 31 31 31
32 32 32 32
33 33 33 33
34 34 34 34
35 35 35 35
36 36 36 36
37 37 37 37
38 38 38 38
39 39 39 39
40 40 40 40
41 41 41 41
    42 42
43 43
44 44
45 45
46 46
47 47
48 48
49 49
50 50
51 51
52 52
53 53
54 54
55 55
56 56
57 57
58 58
59 59
60 60
61 61
62 62
63 63
64 64
65 65
66 66
67 67
68 68
69 69
70 70
71 71
72 72
73 73
74 74
75 75
76 76
77 77
78 78
79 79
80 80
81 81
Table 22.  Full Map
Left Die Right Die
Subsystem Channel I/O Bank I/O Bank Channel Subsystem
2 23 3 0 0 0
2 1
1 2
0 3
22 3 0 1
2 1
1 2
0 3
21 3 0 2
2 1
1 2
0 3
20 3 0 3
2 1
1 2
0 3
19 3 0 4
2 1
1 2
0 3
18 3 0 5
2 1
1 2
0 3
17 3 0 6
2 1
1 2
0 3
16 3 0 7
2 1
1 2
0 3
15 3 0 8
2 1
1 2
0 3
14 3 0 9
2 1
1 2
0 3
13 3 0 10
2 1
1 2
0 3
12 3 0 11
2 1
1 2
0 3
AUX 3 0 AUX
2 1
1 2
0 3
11 3 0 12
2 1
1 2
0 3
10 3 0 13
2 1
1 2
0 3
9 3 0 14
2 1
1 2
0 3
8 3 0 15
2 1
1 2
0 3
7 3 0 16
2 1
1 2
0 3
6 3 0 17
2 1
1 2
0 3
5 3 0 18
2 1
1 2
0 3
4 3 0 19
2 1
1 2
0 3
3 3 0 20
2 1
1 2
0 3
2 3 0 21
2 1
1 2
0 3
1 3 0 22
2 1
1 2
0 3
0 3 0 23
2 1
1 2
0 3
1 23 3 0 0 1
2 1
1 2
0 3
22 3 0 1
2 1
1 2
0 3
21 3 0 2
2 1
1 2
0 3
20 3 0 3
2 1
1 2
0 3
19 3 0 4
2 1
1 2
0 3
18 3 0 5
2 1
1 2
0 3
17 3 0 6
2 1
1 2
0 3
16 3 0 7
2 1
1 2
0 3
15 3 0 8
2 1
1 2
0 3
14 3 0 9
2 1
1 2
0 3
13 3 0 10
2 1
1 2
0 3
12 3 0 11
2 1
1 2
0 3
AUX 3 3 AUX
2 2
1 1
0 0
11 3 0 12
2 1
1 2
0 3
10 3 0 13
2 1
1 2
0 3
9 3 0 14
2 1
1 2
0 3
8 3 0 15
2 1
1 2
0 3
7 3 0 16
2 1
1 2
0 3
6 3 0 17
2 1
1 2
0 3
5 3 0 18
2 1
1 2
0 3
4 3 0 19
2 1
1 2
0 3
3 3 0 20
2 1
1 2
0 3
2 3 0 21
2 1
1 2
0 3
1 3 0 22
2 1
1 2
0 3
0 3 0 23
2 1
1 2
0 3
0 23 3 0 0 2
2 1
1 2
0 3
22 3 0 1
2 1
1 2
0 3
21 3 0 2
2 1
1 2
0 3
20 3 0 3
2 1
1 2
0 3
19 3 0 4
2 1
1 2
0 3
18 3 0 5
2 1
1 2
0 3
17 3 0 6
2 1
1 2
0 3
16 3 0 7
2 1
1 2
0 3
15 3 0 8
2 1
1 2
0 3
14 3 0 9
2 1
1 2
0 3
13 3 0 10
2 1
1 2
0 3
12 3 0 11
2 1
1 2
0 3
AUX 3 3 AUX
2 2
1 1
0 0
11 3 0 12
2 1
1 2
0 3
10 3 0 13
2 1
1 2
0 3
9 3 0 14
2 1
1 2
0 3
8 3 0 15
2 1
1 2
0 3
7 3 0 16
2 1
1 2
0 3
6 3 0 17
2 1
1 2
0 3
5 3 0 18
2 1
1 2
0 3
4 3 0 19
2 1
1 2
0 3
3 3 0 20
2 1
1 2
0 3
2 3 0 21
2 1
1 2
0 3
1 3 0 22
2 1
1 2
0 3
0 3 0 23
2 1
1 2
0 3
3 AUX channel bank 1 (TX only) and bank 2 (RX only) are only 16 data bits wide. Each bank also includes an additional wire for clock.
Level Two Title