Direct Interface Bus (DIB) Intel® Stratix® 10 FPGA IP User Guide

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ID 683142
Date 3/18/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the DIB Intel® Stratix® 10 FPGA IP User Guide 2. About the DIB Intel® Stratix® 10 FPGA IP 3. Functional Description 4. Creating and Parameterizing the Intel FPGA IP 5. Designing with the DIB Intel® Stratix® 10 FPGA IP 6. DIB Intel® Stratix® 10 FPGA IP Interface 7. DIB Intel® Stratix® 10 FPGA IP Parameters 8. Document Revision History for the DIB Intel® Stratix® 10 FPGA IP User Guide A. Die-to-Die Mapping B. Example Pin Locations for One DIB Channel
2. About the DIB Intel® Stratix® 10 FPGA IP x
2.1. Release Information 2.2. Device Support for DIB Intel® Stratix® 10 FPGA IP 2.3. DIB Intel® Stratix® 10 FPGA IP Features 2.4. Latency
3. Functional Description x
3.1. Bypass Mode 3.2. Asynchronous Mode 3.3. Synchronous Mode
3.1. Bypass Mode x
3.1.1. AUX Channel Settings
4. Creating and Parameterizing the Intel FPGA IP x
4.1. IP Catalog and Parameter Editor 4.2. Creating a New Intel® Quartus® Prime Project 4.3. Parameterizing and Generating the IP 4.4. Compiling the DIB Intel® Stratix® 10 FPGA IP Design 4.5. Programming an FPGA Device
5. Designing with the DIB Intel® Stratix® 10 FPGA IP x
5.1. Reset Architecture 5.2. Clocking in Asynchronous and Synchronous Modes 5.3. Timing Closure 5.4. Setting Bypass, Asynchronous, and Synchronous Modes in One DIB Instance
5.2. Clocking in Asynchronous and Synchronous Modes x
5.2.1. Clocking Options 5.2.2. Clock Synchronization
5.3. Timing Closure x
5.3.1. Timing Transfer for Bypass Mode 5.3.2. Timing Transfer for TDM Modes
6. DIB Intel® Stratix® 10 FPGA IP Interface x
6.1. DIB Intel® Stratix® 10 FPGA IP Clocks 6.2. DIB Intel® Stratix® 10 FPGA IP User Interface Signals
1. About the DIB Intel® Stratix® 10 FPGA IP User Guide
2. About the DIB Intel® Stratix® 10 FPGA IP
3. Functional Description
4. Creating and Parameterizing the Intel FPGA IP
5. Designing with the DIB Intel® Stratix® 10 FPGA IP
6. DIB Intel® Stratix® 10 FPGA IP Interface
7. DIB Intel® Stratix® 10 FPGA IP Parameters
8. Document Revision History for the DIB Intel® Stratix® 10 FPGA IP User Guide
A. Die-to-Die Mapping
B. Example Pin Locations for One DIB Channel

3.3. Synchronous Mode

Opt for Synchronous mode if you want the DIB to use your own soft TDM logic.

The Synchronous mode includes the following features:

  • Use this mode when 1:1, 2:1, or 4:1 TDM multiplexing is required with soft TDM logic.
  • The transfer from the DIB to the soft TDM logic is synchronous
  • The DIB clock and system clock have a synchronous relationship.
    • The ratio of the DIB clock and system clock is equal to the TDM ratio.
    • There is no requirement for a system/DUT clock or DIB/DUT clock relationship.
  • The DIB subsystem TDM multiplexers continue to sample and deliver without halting on every dib_clk signal.
  • The soft TDM logic maintains data coherency across dies to ensure that all DUT data is successfully transferred to the other die.
  • You can reduce latency by one clock cycle by turning on the Reduce Sync Mode P2C Latency parameter.
    Note: You may face difficulty in closing timing when you enable this parameter.
  • The RX die generates the system clock for the soft TDM logic on the rem_clk pin.
    • rem_clk is a divided version of dib_clk transmitted from the TX side.
    • The TDM ratio you select in the parameter editor determines the division. For example, TDM ratio 2:1 sets rem_clk to be half of dib_clk.
Figure 9. Synchronous Mode Setup with 4:1 Soft TDM and 2:1 DIB (Hard) TDMThis setup is based on the settings of 4:1 Soft TDM, 2:1 DIB TDM.
Figure 10. Synchronous Mode with 4:1 Soft TDM and 2:1 DIB (Hard) TDM Timing DiagramThis setup is based on the settings of 4:1 Soft TDM, 2:1 DIB TDM.
Figure 11. Synchronous Mode Setup with 4:1 Soft TDM and 4:1 DIB (Hard) TDMThis setup is based on the settings of 4:1 Soft TDM, 4:1 DIB TDM.
Figure 12. Synchronous Mode with 4:1 Soft TDM and 4:1 DIB (Hard) TDM Timing DiagramThis setup is based on the settings of 4:1 Soft TDM, 4:1 DIB TDM, and 1:1 DIB clock.
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